scholarly journals 10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1665
Author(s):  
Paolo Visconti ◽  
Stefano Capoccia ◽  
Eugenio Venere ◽  
Ramiro Velázquez ◽  
Roberto de Fazio
Keyword(s):  
Communication System ◽  
High Speed ◽  
Low Cost ◽  
Scientific Article ◽  
Clock Period ◽  
Data Packets ◽  
Data Throughput ◽  
Field Programmable ◽  
Encryption Decryption ◽  
Base Band

The security of communication and computer systems is an increasingly important issue, nowadays pervading all areas of human activity (e.g., credit cards, website encryption, medical data, etc.). Furthermore, the development of high-speed and light-weight implementations of the encryption algorithms is fundamental to improve and widespread their application in low-cost, low-power and portable systems. In this scientific article, a high-speed implementation of the AES-128 algorithm is reported, developed for a short-range and high-frequency communication system, called Wireless Connector; a Xilinx ZCU102 Field Programmable Gate Array (FPGA) platform represents the core of this communication system since manages all the base-band operations, including the encryption/decryption of the data packets. Specifically, a pipelined implementation of the Advanced Encryption Standard (AES) algorithm has been developed, allowing simultaneous processing of distinct rounds on multiple successive plaintext packets for each clock period and thus obtaining higher data throughput. The proposed encryption system supports 220 MHz maximum operating frequency, ensuring encryption and decryption times both equal to only 10 clock periods. Thanks to the pipelined approach and optimized solutions for the Substitute Bytes operation, the proposed implementation can process and provide the encrypted packets each clock period, thus obtaining a maximum data throughput higher than 28 Gbit/s. Also, the simulation results demonstrate that the proposed architecture is very efficient in using hardware resources, requiring only 1631 Configurable Logic Blocks (CLBs) for the encryption block and 3464 CLBs for the decryption one.

Based on FPGA Intelligent Physiological Parameters Acquisition

2013 ◽  
Vol 344 ◽  
pp. 107-110
Author(s):  
Shun Ren Hu ◽  
Ya Chen Gan ◽  
Ming Bao ◽  
Jing Wei Wang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Physiological Parameters ◽  
Sensor Data ◽  
Low Power Consumption ◽  
Physiological Signal ◽  
Pulse Sensor ◽  
Monitoring Applications ◽  
Field Programmable ◽  
Design Ideas

For the physiological signal monitoring applications, as a micro-controller based on field programmable gate array (FPGA) physiological parameters intelligent acquisition system is given, which has the advantages of low cost, high speed, low power consumption. FPGA is responsible for the completion of pulse sensor, the temperature sensor, acceleration sensor data acquisition and serial output and so on. Focuses on the design ideas and architecture of the various subsystems of the whole system, gives the internal FPGA circuit diagram of the entire system. The whole system is easy to implement and has a very good promotional value.

A Primer for Telemetry Interfacing in Accordance with NASA Standards Using Low Cost FPGAs

2016 ◽  
Vol 05 (01) ◽  
pp. 1640002
Author(s):  
Jake McCoy ◽  
Ted Schultz ◽  
James Tutt ◽  
Thomas Rogers ◽  
Drew Miles ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Photon Counting ◽  
Sounding Rocket ◽  
Photon Counting Detector ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Custom Hardware ◽  
Commercial Off The Shelf ◽  
Main Component

Photon counting detector systems on sounding rocket payloads often require interfacing asynchronous outputs with a synchronously clocked telemetry (TM) stream. Though this can be handled with an on-board computer, there are several low cost alternatives including custom hardware, microcontrollers and field-programmable gate arrays (FPGAs). This paper outlines how a TM interface (TMIF) for detectors on a sounding rocket with asynchronous parallel digital output can be implemented using low cost FPGAs and minimal custom hardware. Low power consumption and high speed FPGAs are available as commercial off-the-shelf (COTS) products and can be used to develop the main component of the TMIF. Then, only a small amount of additional hardware is required for signal buffering and level translating. This paper also discusses how this system can be tested with a simulated TM chain in the small laboratory setting using FPGAs and COTS specialized data acquisition products.

FPGA TECHNOLOGY IN PROCESS TOMOGRAPHY

2016 ◽  
Vol 78 (7-4) ◽  
Author(s):  
Lean Thiam Siow ◽  
Mohd Hafiz Fazalul Rahiman ◽  
Ruzairi Abdul Rahim ◽  
Mohd Shukry Abdul Majid ◽  
Salman Sayyidi Hamzah ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Gate Arrays ◽  
Tomography System ◽  
Process Tomography ◽  
Ultrasonic Process ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Future Work

The aims of this paper are to provide a review of the process tomography applications employing field programmable gate arrays (FPGA) and to understand current FPGA related researches, in order to seek for the possibility to applied FPGA technology in an ultrasonic process tomography system. FPGA allows users to implement complete systems on a programmable chip, meanwhile, five main benefits of applying the FPGA technology are performance, time to market, cost, reliability, and long-term maintenance. These advantages definitely could help in the revolution of process tomography, especially for ultrasonic process tomography and electrical process tomography. Future work is focused on the ultrasonic process tomography for chemical process column investigation using FPGA for the aspects of low cost, high speed and reconstructed image quality.

scholarly journals Space-time trellis codes: Field programmable gate array approach

2020 ◽  
Vol 9 (3) ◽  
pp. 213
Author(s):  
Mallikarjuna Gowda C. P. ◽  
Raju Hajare
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Space Time ◽  
Trellis Codes ◽  
Software Environment ◽  
High Data ◽  
Field Programmable ◽  
Gate Array

This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.

scholarly journals Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1952
Author(s):  
Eva M. Cirugeda-Roldán ◽  
María Sofía Martínez-García ◽  
Alberto Sanchez ◽  
Angel de Castro
Keyword(s):  
High Speed ◽  
Power Converters ◽  
Low Cost ◽  
Hardware In The Loop ◽  
Main Design ◽  
Gate Arrays ◽  
The World ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Area Optimization

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included.

scholarly journals Design and implementation of proposed 320 bit RC6-cascaded encryption/decryption cores on altera FPGA

2020 ◽  
Vol 10 (6) ◽  
pp. 6370
Author(s):  
Ashwaq T. Hashim ◽  
Ahmed M. Hasan ◽  
Hayder M. Abbas
Keyword(s):  
Field Programmable Gate Array ◽  
Block Cipher ◽  
Low Cost ◽  
Structure Design ◽  
Secret Key ◽  
Design And Implementation ◽  
Cryptographic Algorithm ◽  
Field Programmable ◽  
Key Block ◽  
Encryption Decryption

This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.

scholarly journals Area Efficient Implementation of MTI Processing Module on a Reconfigurable Platform

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Munaza Yousuf ◽  
Arshad Aziz ◽  
Riaz Mahmud
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Digital Design ◽  
Radar Signal ◽  
Field Programmable ◽  
Processing Module ◽  
Reconfigurable Platform ◽  
High Level ◽  
High Processing ◽  
Area Efficient

This paper presents an area efficient Field Programmable Gate Array (FPGA) based digital design of a processing module for MTI radar. Signal contaminated with noise and clutter is modelled to test the efficacy of the design algorithms. For flexibility of design and to achieve optimized results, we have combined the high-level utility of MATLAB with the flexibility and optimization on FPGA for this implementation. Two- and three-pulse cancellers are chosen for design due to its simplicity in both concept and implementation. The results obtained are efficient in terms of enhanced throughput per Slice (TPA) of 1.146, that is, occupying fewer area resources on hardware while achieving optimized speed. The outcomes show that this design of MTI radar processor has many advantages, such as high processing precision, strong processing ability, real time, and low cost. All these advantages greatly contribute to the design requirements and make it appropriate for the application of high-speed signal processing.

scholarly journals Low Cost Hardware Architecture of Fast Lifting Wavelet Transform for Image Compression

2019 ◽  
Vol 8 (3) ◽  
pp. 6504-6514
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Critical Path ◽  
Low Cost ◽  
Lifting Wavelet Transform ◽  
Performance Requirements ◽  
Field Programmable ◽  
Hardware Architectures ◽  
Lifting Wavelet ◽  
Hardware Efficiency

In this work, the researchers have given a low-cost, multiplier-less design with latest DWT (2D lifting technology) for high-speed dual-Z scans. A single dimension parallele row, column processors and five transposing registers are the suggested architecture. Furthermore, a 4N timeline buffer is used to process 2D DWT images with NxN resolution. Flipping architecture is intended to decrease the critical path, replacing multipliers with shifting and adding logic. To reduce transposition and latency buffers, dual Z scanning technology is introduced. The proposed architecture is better for similar performance requirements than the existing hardware architectures. Verilog is defined as the suggested Design Register Transfer Logic (RTL) and is synthesized with Xilinx ISE 14.5. When synthesized with a better hardware efficiency for Xilinx Spartan 6 series field programmable gate array, the suggested architecture works at a frequency of 140.47 MHz.

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

Development and production experience of the multilayer curtain-coated linerboard of Ji’an PM No. 3,

TAPPI Journal ◽  
2014 ◽  
Vol 13 (2) ◽  
pp. 17-25
Author(s):  
JUNMING SHU ◽  
ARTHAS YANG ◽  
PEKKA SALMINEN ◽  
HENRI VAITTINEN
Keyword(s):  
Titanium Dioxide ◽  
High Speed ◽  
Food Packaging ◽  
Production Efficiency ◽  
Positive Impact ◽  
Low Cost ◽  
Board Structure ◽  
Flexographic Printing ◽  
Curtain Coating ◽  
Coating Formulations

The Ji’an PM No. 3 is the first linerboard machine in China to use multilayer curtain coating technology. Since successful startup at the end of 2011, further development has been carried out to optimize running conditions, coating formulations, and the base paper to provide a product with satisfactory quality and lower cost to manufacture. The key challenges include designing the base board structure for the desired mechanical strength, designing the surface properties for subsequent coating operations, optimizing the high-speed running of the curtain coater to enhance production efficiency, minimizing the amount of titanium dioxide in the coating color, and balancing the coated board properties to make them suitable for both offset and flexographic printing. The pilot and mill scale results show that curtain coating has a major positive impact on brightness, while smoothness is improved mainly by the blade coating and calendering conditions. Optimization of base board properties and the blade + curtain + blade concept has resulted in the successful use of 100% recycled fiber to produce base board. The optical, mechanical, and printability properties of the final coated board meet market requirements for both offset and flexographic printing. Machine runnability is excellent at the current speed of 1000 m/min, and titanium dioxide has been eliminated in the coating formulations without affecting the coating coverage. A significant improvement in the total cost of coated white liner production has been achieved, compared to the conventional concept of using virgin fiber in the top ply. Future development will focus on combining low cost with further quality improvements to make linerboard suitable for a wider range of end-use applications, including frozen-food packaging and folding boxboard.

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