A Wideband 9 GHz LC-VCO with Tail Current Source Array in 0.18-μm RF CMOS Process

2013 ◽  
Vol 364 ◽  
pp. 434-438
Author(s):  
Peng Ma ◽  
Xiang Ning Fan
Keyword(s):  
Tuning Range ◽  
Supply Voltage ◽  
Current Source ◽  
Cmos Process ◽  
Rf Cmos ◽  
Frequency Bands ◽  
Tail Current ◽  
Start Up ◽  
Source Array ◽  
Lc Vco

A wideband 9 GHz LC-VCO with tail current source array based on TSMC 0.18-μm RF CMOS process is presented in this paper. After discussing the start-up conditions, the structure of tail current source array is utilized to lower the power consumption in high frequency bands and guarantee start-up at low frequency bands. Furthermore, to extend the frequency range, a 4-bit switched capacitor array is used. Based on our analysis, a NMOS cross-coupled VCO with 4-bit PMOS tail current source array is implemented. Post-simulation results show that the tuning range is from 6.372GHz to 9.154GHz and the phase noise at 1MHz offset is less than-110dBc/Hz in the entire tuning range. The operating current of the VCO core is from 8.24mA to 13.362mA in the entire tuning range under 1.8V supply voltage. And the area of the proposed VCO is 1177.775μm × 577.54μm, with two buffer stages and pads.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

Design Methodology of Ultra-Low-Power LC-VCOs for IoT Applications

2019 ◽  
Vol 28 (07) ◽  
pp. 1950122 ◽  
Author(s):  
Imen Ghorbel ◽  
Fayrouz Haddad ◽  
Wenceslas Rahajandraibe ◽  
Mourad Loulou
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Ultra Low Power ◽  
Trade Offs ◽  
Process Measurements ◽  
Lc Vco

A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[Formula: see text][Formula: see text]m CMOS process. Measurements present an ultra-low power consumption of only 262[Formula: see text][Formula: see text]W drawn from 1[Formula: see text]V supply voltage. The measured frequency tuning range is about 10% between 2.179[Formula: see text]GHz and 2.409[Formula: see text]GHz. The post-layout simulation presents a phase noise (PN) of [Formula: see text][Formula: see text]dBc/Hz, while the measured PN is [Formula: see text][Formula: see text]dBc/Hz.

scholarly journals Low-Power Two-Phase Clocking Adiabatic PUF Circuit

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1258
Author(s):  
Câncio Monteiro ◽  
Yasuhiro Takahashi
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Process Variations ◽  
The Body ◽  
Cmos Process ◽  
Clock Signal ◽  
Process Technology ◽  
Two Phase ◽  
Ambient Temperatures ◽  
Start Up

Internet of Things (IoT) has enabled battery-powered devices to transmit sensitive data, while presenting high power consumption and security issues. To address these challenges, adiabatic-based physical unclonable functions (PUFs) offer a promising solution for low-power and secure IoT device applications. In this study, we propose a novel low-power two-phase clocking adiabatic PUF. The proposed adiabatic PUF utilizes a trapezoidal power clock signal with a time-ramped voltage to achieve an improved energy efficiency and reliable start-up PUF behavior. Static CMOS logic is employed to produce stable challenge-response pairs (CRPs) in the adiabatic mode. The pull-down network is designed to control the PUF cell to charge and discharge its output nodes with a constant supply current during secure key generation. The body effect of PMOS transistors, ambient temperatures, and CMOS process variations are investigated to examine the uniqueness and reliability of the proposed work. The proposed adiabatic PUF is simulated using 0.18 µm CMOS process technology with a supply voltage of 1.8 V. The uniqueness and reliability of the proposed adiabatic PUF are 49.82% and 99.47%, respectively. In addition, it requires a start-up power of 0.47 µW and consumes an energy of 15.98 fJ/bit/cycle at the reference temperature of 27 °C.

scholarly journals DESIGN AND INVESTIGATION OF 65 NM RF CMOS TECHNOLOGY LC-VCO’S / AUKŠTADAŽNIŲ, 65 NM KMOP TECHNOLOGIJOS, LC ĮTAMPA VALDOMŲ GENERATORIŲ PROJEKTAVIMAS IR TYRIMAS

2014 ◽  
Vol 6 (2) ◽  
pp. 198-201 ◽  
Author(s):  
Vytautas Mačaitis ◽  
Vaidotas Barzdėnas
Keyword(s):  
Power Dissipation ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Rf Cmos ◽  
Voltage Controlled Oscillators ◽  
Capacitor Array ◽  
Layout Area ◽  
Offset Frequency

In this paper, two LC Voltage-Controlled Oscillators (LC-LC-VCO1 and LC-VCO2) are designed using TSMC 65 nm LP/MS/RF CMOS technology. Two arrays, one of which is a 6-bit capacitor array and the other – an array of MOS varactors, provide a wide LC-VCO frequency tuning range. Post-layout simulation results unveiled that at 1.8 V supply voltage the tuning range of LC-VCO1 spans from 5.17 GHz to 6.76 GHz and for LC-VCO2 the range spans from 6.33 GHz to 8.08 GHz. The phase noise at 1 MHz offset frequency is about −123.1 dBc/Hz for LC-VCO1 and −121.6 dBc/Hz for LC-VCO2. The power dissipation at maximum carrier is 30.47 mW for LC-VCO1 and 30.5 mW for LC-VCO2. The layout area is 285×335 μm and 255×305 μm, respectively for LC-VCO1 and LC-VCO2. Straipsnyje nagrinėjami ir projektuojami LC įtampa valdomi generatoriai (LC-ĮVG), plačiai taikomi šiuolaikiniuose daugiastandarčiuose ir daugiajuosčiuose siųstuvuose-imtuvuose. Naudojant TSMC kompanijos 65 nm LP/MS/RF KMOP inte­grinių grandynų gamybos technologiją suprojektuoti ir išanalizuoti du skirtingų dažnio diapazonų LC-ĮVG. Generuojamas dažnis yra valdomas dviem būdais, t. y. galimas apytikslis bei tikslus dažnio nustatymas. Norint apytiksliai nustatyti dažnį naudojamas 6 bitais skaitmeniškai valdomas perjungiamų kondensatorių blokas, o norint tiksliai parinkti valdymą – NMOP varaktorių blokas. Kompiuterinio modeliavimo metu gauti tokie pagrindiniai LC-ĮVG parametrai: valdomo dažnio diapazonas – nuo 5,17 GHz iki 6,76 GHz (LC-ĮVG1) ir nuo 6,33 GHz iki 8,08 GHz (LC-ĮVG2); fazinis triukšmas, esant 1 MHz poslinkio dažniui ir maksimaliam nešlio dažniui: –123,1 dBc/Hz (LC-ĮVG1) ir –121,6 dBc/Hz (LC-ĮVG2); vartojamoji galia, esant maksimaliam nešlio dažniui: –30,47 mW (LC-ĮVG1) ir 30,5 mW (LC-ĮVG2). Suprojektuotų LC-ĮVG1 ir LC-ĮVG2 topologijų plotas yra atitinkamai lygus 0,078 mm2 ir 0,096 mm2.

12-BIT PSEUDO-DIFFERENTIAL CURRENT-SOURCE RESISTOR-STRING HYBRID DAC

2011 ◽  
Vol 20 (04) ◽  
pp. 709-725 ◽  
Author(s):  
M. T. S. AB-AZIZ ◽  
A. MARZUKI ◽  
Z. A. A. AZIZ
Keyword(s):  
Supply Voltage ◽  
Current Source ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Process Technology ◽  
Analog Converter ◽  
Final Design ◽  
Resistor String ◽  
Simulation Results ◽  
Binary Weighted

This paper discusses a hybrid Digital-Analog Converter (DAC) architecture which is a combination of a binary-weighted resistor approach for eight bits in the least-significant-bit and thermometer coded approach for four bits in the most-significant-bit. The proposed design combines advantages of the binary-weighted resistor approach and thermometer coded approach. The final design is composed of two 12-bit DACs to achieve a pseudo differential output signal. The converter was designed with a Silterra 0.18 μm 1.8 V/3.3 V CMOS process technology. The post-layout simulation results show that this design achieves 12-bit resolution with INL and DNL of 0.375 LSB and 0.25 LSB, respectively. The power consumption is 6.291 mW when the designed DAC is biased with supply voltage equal to 3 V. The performance is accomplished with a design area of 230 μm × 255 μm.

A VERY LOW-TC SECOND-ORDER TEMPERATURE-COMPENSATED CMOS CURRENT REFERENCE

2014 ◽  
Vol 23 (03) ◽  
pp. 1450042 ◽  
Author(s):  
LIANG LIANG ◽  
ZHANGMING ZHU ◽  
YINTANG YANG
Keyword(s):  
Temperature Compensation ◽  
Supply Voltage ◽  
Design Method ◽  
Current Source ◽  
Second Order ◽  
Cmos Process ◽  
Current Mirror ◽  
First Order ◽  
Temperature Range ◽  
Current Reference

This paper proposes a novel second-order temperature-compensated CMOS current reference which exploits a new self-biased current source for first-order temperature compensation and a resistor-free widlar current mirror for second-order temperature compensation. Moreover, by deriving the temperature coefficient (TC) of the reference current, the temperature compensation condition equations together with a design method of minimizing the thermal drift in a required temperature range are presented. Based on these, the circuit is designed in a standard 0.18 μm CMOS process and achieves a very low TC of only 16.9 ppm/°C in a temperature range between -40°C and 120°C, with 1 μA reference current at 27°C. Besides, the current reference can operate at supply voltage down to 1.3 V, with a good supply regulation of 0.5%/V. At 27°C, its power consumption is 8.93 μW.

scholarly journals A 0.026 mm2 Time Domain CMOS Temperature Sensor with Simple Current Source

Micromachines ◽  
2020 ◽  
Vol 11 (10) ◽  
pp. 899 ◽  
Author(s):  
Sangwoo Park ◽  
Sangjin Byun
Keyword(s):  
Time Domain ◽  
Temperature Sensor ◽  
Feedback Loop ◽  
Supply Voltage ◽  
Current Source ◽  
Cmos Process ◽  
Voltage Sensitivity ◽  
Temperature Dependent ◽  
Digital Conversion ◽  
Pmos Transistor

This paper presents a time domain CMOS temperature sensor with a simple current source. This sensor chip only occupies a small active die area of 0.026 mm2 because it adopts a simple current source consisting of an n-type poly resistor and a PMOS transistor and a simple current controlled oscillator consisting of three current starved inverter delay cells. Although this current source is based on a simple architecture, it has better temperature linearity than the conventional approach that generates a temperature-dependent current through a poly resistor using a feedback loop. This temperature sensor is designed in a 0.18 μm 1P6M CMOS process. In the post-layout simulations, the temperature error was measured within a range from −1.0 to +0.7 °C over the temperature range of 0 to 100 °C after two point calibration was carried out at 20 and 80 °C, respectively. The temperature resolution was set as 0.32 °C and the temperature to digital conversion rate was 50 kHz. The energy efficiency is 1.4 nJ/sample and the supply voltage sensitivity is 0.077 °C/mV at 27 °C while the supply voltage varies from 1.65 to 1.95 V.

scholarly journals A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers

2011 ◽  
Vol 2011 ◽  
pp. 1-7 ◽  
Author(s):  
Yusaku Ito ◽  
Kenichi Okada ◽  
Kazuya Masu
Keyword(s):  
Tuning Range ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Variable Gain ◽  
Continuous Frequency ◽  
Reconfigurable Radio ◽  
Lc Vco

This paper proposes a novel wideband LC-based voltage-controlled oscillator (VCO) for multistandard transceivers. The proposed VCO has a core LC-VCO and a tuning-range extension circuit, which consists of switches, a mixer, dividers, and variable gain combiners with a spurious rejection technique. The experimental results exhibit 0.98 to 6.6 GHz continuous frequency tuning with −206 dBc/Hz of FoMT, which is fabricated by using a 0.18 μm CMOS process. The frequency tuning range (FTR) is 149%, and the chip area is 800 μm × 540 μm.

scholarly journals Transition Frequencies and Negative Resistance of Inductively Terminated CMOS Buffer Cell and Application in MMW LC VCO

2010 ◽  
Vol 2010 ◽  
pp. 1-11 ◽  
Author(s):  
S. M. Rezaul Hasan
Keyword(s):  
Supply Voltage ◽  
Noise Analysis ◽  
Negative Resistance ◽  
Geometrical Parameters ◽  
Cmos Process ◽  
Process Technology ◽  
Shunt Resistance ◽  
Low Power Dissipation ◽  
Cell Changes ◽  
Lc Vco

This paper investigates the transition frequencies () of an inductively terminated CMOS source follower buffer for negative resistance behavior at which the effective shunt resistance looking into the source of the buffer cell changes sign. Possible limiting frequencies of oscillation are determined based on resonators formed by a grounded gate inductor and a parasitic capacitance at the gate of the negative resistance buffer cell. The range of frequencies of oscillation of this negative resistance buffer cell for variations in the different circuit parameters/elements is explored. Following this, a millimeter wave (MMW) oscillator is simulated using the IBM 130 nm CMOS process technology which can operate at 70 GHz. High-frequency MOSFET model was used for these simulations. The cell had an extremely low power dissipation of under 3 mW. Extensive Monte Carlo simulations were carried out for manufacturability analysis considering up to 50% variation in process and geometrical parameters, supply voltage, and ambient temperature. Noise analysis and a simulated estimate of the phase noise in an MMW LC VCO application is also reported.

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