Removal Characteristics of Hillock Defects on Silicon Substrate by Chemical Uniformity Etching Enhanced Polishing Slurry

2012 ◽  
Vol 452-453 ◽  
pp. 219-222
Author(s):  
Ming Sun ◽  
Juan Wang ◽  
Ru Wang ◽  
Yu Ling Liu ◽  
Li Bing Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Silicon Wafer ◽  
High Speed ◽  
Removal Rate ◽  
Life Time ◽  
Lower Surface ◽  
Surface Strain ◽  
Chemical Additives ◽  
Chemical Etch ◽  
High Removal Rate

The thermally generated defects will lower the life time in bulk silicon and cause increasing in the leakage current of individual diodes in integrated circuits, that will finally cause the malfunction with advanced devices and IC chips. The removal characteristics of hillock defects on the single bare silicon wafer generated by the thermal process were experimentally analysed with respect to the chemical additives enhanced uniform chemical etching and mechanical abrasion of high pure nano sphere colloidal silica interplaying with the alkali based polishing slurry. During the polishing, it was found that the silicon surface contacted with high speed of rotated polishing pad under the down force pressure is chemically dissolved by the slurry containing FA/O organic polyamine(R(NH2)n) agent with adding proper proportional FA/O I non ions surfactant, which effectively lowered the surface strain of slurry contacted to the reactive surface of the wafer and slurry enhanced uniform chemical etch leading to the hillock region and no hillock region. However, by the process of chemical mechanical polishing，the results show it can eliminate the hillock defects on the surface of silicon wafer thoroughly with high removal rate, and achieve lower surface roughness than before process of polishing.

A Novel Tape and Diamond Process Developed for Polishing Hard Substrates

2015 ◽  
Vol 656-657 ◽  
pp. 416-421
Author(s):  
Rong Hwei Yeh ◽  
T.M. Chao ◽  
Cheng Kuo Lee ◽  
A.H. Tan
Keyword(s):  
Surface Roughness ◽  
Removal Rate ◽  
Lower Surface ◽  
Polished Surface ◽  
Closed Chamber ◽  
Glass Substrates ◽  
Nominal Size ◽  
Hard Glass ◽  
High Removal Rate ◽  
Diamond Abrasive

A nanoscale polish process with improved desired characteristics of low roughness and low scratch counts has been developed using a novel polish tape and diamond abrasive on hard glass substrates. For an improved polishing performance with high removal rate properties and preventing scratches, a novel tape was developed having a nanofiber level, densified surface and a flatter surface by slenderizing the fiber and dispersing ultrafine fiber using an innovative technique. Using this novel polishing tape with a fiber size of 200nm, one can produce a 17% lower surface roughness (Ra) (from 1.05A to 0.87A) and a reduced polished surface scratch count of 53 reduced to 18. The novel nanocluster diamond abrasive is synthesized from carbon atoms of explosives created by detonation in a closed chamber under an oxygen leaked atmosphere ambient. Several crystals are bonded together by layers of non-diamond carbon and other elements, forming aggregates with a nanocluster structure. Using this novel nanocluster diamond along with an ultra-fine diamond mixture with a nominal size of 15nm, one is able to produce an improvement of a 48% lower surface roughness Ra (from 0.87A to 0.45A) and a lower polishing surface scratch count reduced from 18 to 7. Overall, these results indicate that a smoother and a reduced scratch polished substrate results in a significant improvement in disk defects and related magnetic performances.

Chatter Vibration Modeling in High Speed Milling Operations

2008 ◽  
Author(s):  
Giuseppe Catania ◽  
Nicolo` Mancinelli
Keyword(s):  
High Speed ◽  
Removal Rate ◽  
Lumped Parameter Model ◽  
Beam Shape ◽  
Stability Lobe ◽  
Milling Operations ◽  
Excited Vibration ◽  
Cutting Force Components ◽  
The Stability ◽  
High Removal Rate

High removal rate in milling operations can be limited by chatter occurrence. Several studies on this self-excited vibration can be found in the literature: simple models (1 or 2 dofs) are proposed, i.e. a lumped parameter model of the milling machine being excited by regenerative, time-varying cutting forces. In this study, the machine tool spindle was modeled by a discrete modal approach, based on the continuous beam shape, analytical eigenfunctions, while the eigenvalues were mainly experimentally identified. The regenerative cutting force components lend to a set of Delay Differential Equations (DDEs) with periodic coefficients; DDEs were numerically integrated for different machining conditions. The stability lobe chart was evaluated using the semi-discretization method. Time histories, spectra and Poincare´ maps related to the vibratory behavior of the system were numerically obtained and differences with respect to the bifurcations predicted by the simplest models known in literature are pointed out. Some different behaviors in the shape of the stability lobe charts and in the spectra of the chatter vibrations were also observed.

Surfactants in Controlling Removal Rates and Selectivity in Barrier Slurry for Cu CMP

2007 ◽  
Vol 991 ◽  
Author(s):  
Jinru Bian
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Removal Rate ◽  
Leading Edge ◽  
Dielectric Surface ◽  
Wafer Surface ◽  
Capping Layer ◽  
Charge Interaction ◽  
High Removal Rate ◽  
Low K

ABSTRACTLeading edge integrated circuits (ICs) are complicated structures designed to have up to 3 capping layers above a low k dielectric material. The upper capping layer may use TEOS and/or silicon nitride (SiN), while the lower one may use silicon carbon nitride (SiCN), silicon carbide (SiC), or carbon doped oxide (CDO) immediately above the low k dielectric. Therefore, a barrier slurry for copper CMP, in addition to exhibiting a high removal rate of the barrier, must be able to remove the upper capping layer and stop at the underlying dielectric surface.We have developed a slurry family that can effectively remove TaN, TEOS, SiN, CDO, and/or SiCN, or any combination of these films, or can stop at any one or two film surfaces of TEOS, SiN, CDO, SiCN, and SiC, depending on the specific slurry design. Removal rate control is achieved by one or two additives. One of the additives is an anionic surfactant. When selecting a surfactant, the surfactant hydrophobicity and charge interaction between the surfactant and the wafer surface are two important factors to be considered. This report discusses these two factors in selecting a proper surfactant for a specific slurry application.

Application and Development of High-Efficiency Abrasive Finishing

2011 ◽  
Vol 189-193 ◽  
pp. 3113-3116
Author(s):  
Chang He Li ◽  
Ling Yun Qi ◽  
Hua Yang Zhao
Keyword(s):  
High Speed ◽  
High Performance ◽  
High Efficiency ◽  
Removal Rate ◽  
Grinding Wheel ◽  
Abrasive Machining ◽  
Machining Processes ◽  
Belt Grinding ◽  
Hard And Brittle Materials ◽  
High Removal Rate

High-efficiency abrasive machining is one of the important technology of advanced manufacture. Combined with raw and finishing machining, it can attain high removal rate like turning, milling and planning. The difficult-to-grinding materials can also be ground by means of this method with high performance. In the present paper, development status and latest progresses on high efficiency abrasive machining technologies relate to high speed and super-high speed grinding, high efficiency deep-cut grinding, hard and brittle materials high-efficiency grinding, powerful grinding and belt grinding were summarized. The efficiency and parameters range of these abrasive machining processes were compared. The key technologies of high efficiency abrasive machining, including grinding wheel, spindle and bearing, grinder, coolant supplying, installation and orientation of wheel and workpiece and safety defended, as well as intelligent monitor and NC grinding were investigated.

Cause of Etch Pits during the High Speed Plasma Etching of Silicon Carbide and an Approach to Reduce their Size

2020 ◽  
Vol 1004 ◽  
pp. 161-166
Author(s):  
Yuma Nakanishi ◽  
Risa Mukai ◽  
Satoshi Matsuyama ◽  
Kazuto Yamauchi ◽  
Yasuhisa Sano
Keyword(s):  
Silicon Carbide ◽  
High Pressure ◽  
Plasma Etching ◽  
High Speed ◽  
Removal Rate ◽  
Etch Pits ◽  
Power Transistors ◽  
Pressure Plasma ◽  
Device Processing ◽  
High Removal Rate

To reduce the on-resistance in vertical power transistors, backside thinning is required after device processing. However, it is difficult to thin silicon carbide (SiC) wafers with a high removal rate by conventional mechanical processing because their hardness and brittleness cause cracks and chips during thinning. Therefore, the authors have attempted to thin SiC wafers using plasma chemical vaporization machining (PCVM), which is plasma etching using high-pressure plasma. PCVM has a high removal rate because of the high radical density in the high-pressure plasma, and it does not form a damaged layer on the processed surface because of the low ion energy. The authors have already achieved a very high removal rate of 15.6 μm/min by PCVM. However, many etch pits were generated on the wafer during PCVM in these high-speed machining conditions. Therefore, this study, using molten potassium hydroxide (KOH) etching, investigated the cause of such etch pits and found that they may stem from threading screw dislocation in the wafers. In addition, this research considered a process for reducing an etch pit size and succeeded in doing so by controlling wafer temperature.

The CMP by Polishing with GiP Dressed by BODD

2010 ◽  
Vol 126-128 ◽  
pp. 1013-1018 ◽  
Author(s):  
James C. Sung ◽  
Ming Yi Tsai ◽  
Cheng Shiang Chou ◽  
Pei Lum Tso ◽  
Ying Tung Chen
Keyword(s):  
High Speed ◽  
Removal Rate ◽  
Continual Improvement ◽  
Graphite Particles ◽  
Cost Of Ownership ◽  
High Removal Rate ◽  
Wafer Surfaces

Due to the continual improvement of CMP technologies, and the need for polishing delicate wafers at high speed, graphite impregnated pads (GiP) dressed by brazed organic dia mond disks (BODD) can double the throughput of wafer-pass at the reduced cost of ownership (CoO). The increased polishing rate is due to the act of nano graphite particles that absorb slurry. The nano graphite particles coated with chemical and abrasive can achieve high removal rate without causing scratches on the wafer. In addition, nano graphite particles do not stick to wafer surfaces, so they can be cleaned easily. BODD can uniquely dress GiP to create slurry channels so the pore free pad is not bottlenecked by slurry supply. This paper also demonstrated the low stress polishing by applying ultrasound during the CMP process.

Surface Quality of Finishing Cut by WEDM in Gas

2007 ◽  
Vol 24-25 ◽  
pp. 91-96
Author(s):  
Tong Wang ◽  
Xin Fu Zhang ◽  
Xue Fang Zhao ◽  
M. Kunieda
Keyword(s):  
Surface Quality ◽  
High Speed ◽  
Electrochemical Etching ◽  
Removal Rate ◽  
Low Speed ◽  
The Wire ◽  
High Removal Rate ◽  
Discharge Gap

This paper studies on a newly developed method, WEDM in gas, and discribes the features of finishing dry-WEDMed surface, such as narrower discharge gap length, higher surface straightness accuracy and no electrochemical etching actions. Low-speed WEDM removal rate in gas can be improved by increasing the wire winding speed. High-speed WEDM in gas has a significant advantage as high removal rate beyond the abovementioned good points, which is available for improving conventional high-speed WEDM quality.

The Effects of Strong Oxidizing Slurry and Processing Atmosphere on Double-Sided CMP of SiC Wafer

2012 ◽  
Vol 591-593 ◽  
pp. 1131-1134 ◽  
Author(s):  
Tao Yin ◽  
Toshiro Doi ◽  
Syuhei Kurokawa ◽  
Osamu Ohnishi ◽  
Tsutomu Yamazaki ◽  
...  
Keyword(s):  
Atmospheric Pressure ◽  
High Speed ◽  
Removal Rate ◽  
The Other ◽  
High Quality ◽  
Air Atmosphere ◽  
Other Hand ◽  
New Type ◽  
High Removal Rate ◽  
Sic Wafer

In order to achieve high removal rate and high-quality processing on SiC wafer, we carried out the CMP processing experiment with the new type CMP machine (Bell-jar) by using the slurry with the addition of strong oxidant (KMnO4). It was found that the high speed CMP processing was achieved by controlling the concentration of KMnO4 in the slurry, the pH of slurry and the processing atmosphere. By using the slurry with the addition of KMnO4 of 0.1mol/L, the removal rate was the fastest up to 1019nm/h in the fixed pH of 6. By use of the slurry of pH 3, the removal rate of C-face of SiC wafer was 1695nm/h On the other hand, the fastest removal rate of Si-face of SiC wafer was only 51nm/h by using the slurry whose pH is 7. In the open air atmosphere, the removal rate was 915nm/h, which was higher than that at the higher and lower atmospheric pressure.

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

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