scholarly journals A Power Efficient Self Biased OTA Design Based on g_m/I_D Methodology with Considering Load Variation, Temperature Variation and Power Supply Variation

2018 ◽  
Vol 7 (2) ◽  
pp. 104
Author(s):  
Vikas Mittal
Keyword(s):  
Power Supply ◽  
High Frequency ◽  
Design Methodology ◽  
Cmos Technology ◽  
Temperature Variations ◽  
Power Efficient ◽  
Load Variations ◽  
Current Consumption ◽  
Rf Communication ◽  
Simulation Results

The present work addresses the design of power efficient fully self biased OTA using a design methodology based on the  transistor characteristics. This analog module was analyzed, designed and prototyped in TSMS 0.35μm CMOS technology. Simulation results are presented, in order to validate the methodology. The OTA has Gain of 41.35 dB and 3db bandwidth of 138.73 kHz and the UGB of 12.40MHz with the current consumption of 65.50 μA. The circuit does not have need of any DC external biasing circuit, only need to apply VDD (3.3 V). Here self biasing has been introduced with power consumption of 216.15μW. The results have been taken with load variations, temperature variations, and power supply variations. This circuit used in real time high frequency applications as in RF communication.

Common Mode Feedback Circuits for Low Voltage Fully-Differential Amplifiers

2016 ◽  
Vol 25 (10) ◽  
pp. 1650124 ◽  
Author(s):  
S. Rekha ◽  
T. Laxminidhi
Keyword(s):  
Power Supply ◽  
Continuous Time ◽  
Efficient Solution ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Power Efficient ◽  
Differential Amplifiers ◽  
Fully Differential ◽  
Simulation Results

Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5[Formula: see text]V in 0.18[Formula: see text][Formula: see text]m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1[Formula: see text]fF to tens of femto farads.

An Analytical Study on Jitter Accumulation in Interleaved Phase Frequency Detectors for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 534 ◽  
pp. 197-205
Author(s):  
Kiichi Niitsu ◽  
Masato Sakurai ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Daiki Oki ◽  
...  
Keyword(s):  
Power Supply ◽  
Analytical Study ◽  
Cmos Technology ◽  
High Accuracy ◽  
Spice Simulation ◽  
Supply Noise ◽  
Noise Injection ◽  
Simulation Results ◽  
On Chip ◽  
Frequency Detector

This work presents the analytical study on jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. Jitter accumulation in phase frequency detector degrades the accuracy of on-chip jitter measurements, and required to be mitigated. In order to analyze and estimate the jitter accumulation in phase frequency detectors, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that, with a 50 mV power supply noise injection, jitter accumulation can be reduced from 1.03 ps to 0.49 ps (52% reduction) by using an interleaved architecture.

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

AN EFFICIENT LOW-POWER SIGMA-DELTA MODULATOR FOR MULTI-STANDARD WIRELESS APPLICATIONS

2012 ◽  
Vol 21 (04) ◽  
pp. 1250028 ◽  
Author(s):  
B. HODA SEYEDHOSSEINZADEH ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Cmos Technology ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Wireless Applications ◽  
Design And Implementation ◽  
Simulation Results ◽  
System Level Simulations

This paper describes the design and implementation of a reconfigurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5 MHz, 10 MHz, 1.92 MHz, 0.5 MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5 mW using a single 1 V power supply.

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

Design Methodology and Jitter Analysis of a Delay Line for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 596 ◽  
pp. 176-180
Author(s):  
Kiichi Niitsu ◽  
Kazunori Sakuma ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Nobukazu Takai ◽  
...  
Keyword(s):  
Design Methodology ◽  
Thermal Noise ◽  
Delay Line ◽  
Cmos Technology ◽  
High Accuracy ◽  
Delay Lines ◽  
Spice Simulation ◽  
Simulation Results ◽  
On Chip

This work presents the design methodology and jitter analysis of a delay line for high-accuracy on-chip jitter measurements. Jitter generated in the delay lines degrades the accuracy of on-chip jitter measurements, and required to be minimized. In order to analyze and the jitter generation in the delay lines, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that jitter due to thermal noise can be reduced by enlarging the transistor sizes of both PMOS and NMOS. Based on the results, design methodology of a delay line is introduced for minimizing the jitter generation.

Research of Compensated AC Regulated Power Supply in Electric Power Systems Based on a High-Frequency Isolated Transformer

2013 ◽  
Vol 676 ◽  
pp. 227-230
Author(s):  
Qi Liang Zhang ◽  
Ping Wang ◽  
Liu Yang
Keyword(s):  
Power Systems ◽  
Electric Power ◽  
Power Supply ◽  
High Frequency ◽  
Output Voltage ◽  
Closed Loop ◽  
Electric Power Systems ◽  
Slow Response ◽  
Voltage Fluctuation ◽  
Simulation Results

In this paper, a new topology of compensated AC regulated power supply (ACRPS) in electric power systems based on a high-frequency isolated transformer (HFIT) is proposed. In order to overcome the slow response and low accuracy of the existing ACRPS, the phase shift regulating control (PSRC) based on instantaneous value of voltage single closed loop is applied as well as the software phase locked loop (SPLL). The proposed ACRPS has been simulated in the case of the voltage fluctuation, harmonics and frequency shift with Matlab. The simulation results show that output voltage precision is controlled within 0.5% and total harmonic distribution (THD) can be limited to less than 1%. In a word, the feasibility of the proposed ACRPS is effectively verified.

ON-CHIP POWER-EFFICIENT CURRENT FLATTENING CIRCUIT

2009 ◽  
Vol 18 (03) ◽  
pp. 565-579 ◽  
Author(s):  
HALEH VAHEDI ◽  
STEFANO GREGORI ◽  
RADU MURESAN
Keyword(s):  
Integrated Circuits ◽  
Smart Card ◽  
Power Supply ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Control Circuit ◽  
Smart Cards ◽  
Portable Devices ◽  
Chip Area ◽  
Power Efficient

This paper presents a control circuit which regulates the current consumption of integrated circuits using current injection and voltage scaling techniques. The control circuit can be integrated with smart cards as a countermeasure against power analysis attacks and electromagnetic emanation analysis attacks. We have designed the proposed circuit in 0.18 μm CMOS technology at 1.8 V power supply. The simulation results show that the circuit controls the current through the power supply pin of a model of a smart card microcontroller and attenuates the peak-to-peak current variations by 95%. The power dissipation overhead of the control circuit is less than 20% of the original power dissipation of the smart card microcontroller. Comparing the layout area of the proposed circuit with that of an ASIC 3-DES algorithm in the same technology shows that the control circuit only constitutes 4% of the cryptographic processor. The proposed circuit proves to be especially useful for smart cards and small portable devices, where power dissipation and chip area are critical.

Designing LC VCOs Using Capacitive Degeneration Techniques

2005 ◽  
Vol 15 (02) ◽  
pp. 319-351 ◽  
Author(s):  
Byunghoo Jung ◽  
Ramesh Harjani
Keyword(s):  
High Frequency ◽  
Oscillation Frequency ◽  
Tuning Range ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Wide Tuning Range ◽  
Test Vehicle ◽  
Bicmos Technology ◽  
Simulation Results ◽  
Degeneration Techniques

In this paper, we present a detailed analysis of VCOs using a capacitively degenerated negative resistance cell. The negative resistance cell using capacitive degeneration has a higher maximum attainable oscillation frequency and a smaller equivalent shunt capacitance when compared to the widely used cross-coupled negative-gm cell. These properties are of particular interest for the design of high-frequency and/or wide tuning range VCOs. The negative resistance provided by a traditional capacitively degenerated negative resistance cell is lower than that provided by a cross-coupled negative-gm cell. We present an active capacitive degeneration topology that overcomes this limitation. To validate this circuit topology we use two test vehicles. The first test vehicle is a 5.3 GHz VCO designed in a 0.25 μm CMOS technology and the second test vehicle is a 20 GHz VCO designed in a 0.25 μm BiCMOS technology. Measurement and simulation results from both test vehicles effectively demonstrate the efficacy of the capacitive degeneration technique.

scholarly journals Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects

VLSI Design ◽  
1997 ◽  
Vol 5 (3) ◽  
pp. 273-284 ◽  
Author(s):  
Victor H. Champac ◽  
Joan Figueras
Keyword(s):  
Experimental Data ◽  
Power Supply ◽  
Floating Gate ◽  
Combinational Circuits ◽  
Current Testing ◽  
Current Consumption ◽  
Supply Current ◽  
Simulation Results ◽  
Good Agreement

The behavior of basic CMOS combinational gates in the presence of a floating gate defect is characterized in order to investigate its detectability by IDDQ . The defect is modeled at the circuit level by the poly-bulk and metal-poly capacitances, which determine the quiescent power supply current consumption (IDDQ ) of the defective circuit. The testing implications on the type of defective gate are studied. Experimental measures have been made on basic CMOS combinational modules designed with intentional floating gate defects. A good agreement is observed between the simulation results and the experimental data. A conventional ATPG for stuck-at faults is used to obtain the required exciting vector to test the floating gate defects by IDDQ Testing.

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