Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask

2006 ◽  
Vol 527-529 ◽  
pp. 1203-1206 ◽  
Author(s):  
Takeyoshi Masuda ◽  
Kazuhiro Fujikawa ◽  
Kaoru Shibata ◽  
Hideto Tamaso ◽  
Satoshi Hatsukawa ◽  
...  
Keyword(s):  
Electric Field ◽  
Ion Implantation ◽  
Fabrication Process ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Dry Process ◽  
Metal Mask ◽  
Surface Field ◽  
Reduced Surface

We fabricated 4H-SiC lateral JFETs with a reduced surface field (RESURF) structure, which can prevent the concentration of electric field at the edge of the gate metal [1]. Previously, we reported on the 4H-SiC RESURF JFET with a gate length (LG) of 10 μm [2]. Its specific on-resistance was 50 mΩcm2, which was still high. Therefore, a Ti/W layer was used as an ion implantation mask so as to decrease the thickness of the mask and to improve an accuracy of the device process. A RESURF JFET with the gate length (LG) of 3.0 μm was fabricated, and the specific on-resistance of 6.3 mΩcm2 was obtained. In this paper, the fabrication process and the electrical characteristics of the device are described.

Switching the electrical characteristics of TiO2 from n-type to p-type by ion implantation

2021 ◽  
pp. 150274
Author(s):  
Adriano Panepinto ◽  
Arnaud Krumpmann ◽  
David Cornil ◽  
Jérôme Cornil ◽  
Rony Snyders
Keyword(s):  
Ion Implantation ◽  
Electrical Characteristics ◽  
P Type

Scanned Electron Beam Annealing of Boron-Implanted Diodes

1980 ◽  
Vol 1 ◽  
Author(s):  
T. O. Yep ◽  
R. T. Fulks ◽  
R. A. Powell
Keyword(s):  
Electron Beam ◽  
Ion Implantation ◽  
Reverse Bias ◽  
Carrier Lifetime ◽  
Reverse Current ◽  
Electrical Activation ◽  
Electrical Characteristics ◽  
Low Resolution ◽  
Implantation Damage ◽  
Dopant Redistribution

ABSTRACTSuccessful annealing of p+ n arrays fabricated by ion-implantation of 11B (50 keV, 1 × 1014 cm-2) into Si (100 has been performed using a broadly rastered, low-resolution (0.25-inch diameter) electron beam. A complete 2" wafer could be uniformly annealed in ≃20 sec with high electrical activation (>75%) and small dopant redistribution (≃450 Å). Annealing resulted In p+n junctions characterized by low reverse current (≃4 nAcm-2 at 5V reverse bias) and higher carrier lifetime (80 μsec) over the entire 2" wafer. Based on the electrical characteristics of the diodes, we estimate that the electron beam anneal was able to remove ion implantation damage and leave an ordered substrate to a depth of 5.5 m below the layer junction.

scholarly journals Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology

2018 ◽  
Vol 201 ◽  
pp. 02004
Author(s):  
Shao-Ming Yang ◽  
Gene Sheu ◽  
Tzu Chieh Lee ◽  
Ting Yao Chien ◽  
Chieh Chih Wu ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
High Voltage ◽  
High Performance ◽  
Power Device ◽  
Simulation Tool ◽  
Process Technology ◽  
Surface Field ◽  
Kirk Effect ◽  
Tcad Simulation ◽  
Reduced Surface

High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also proposed a better performance of both device without kirk effect.

In situ electric field perturbations of deep trap accumulation in silicon during proton ion implantation

1995 ◽  
Vol 66 (13) ◽  
pp. 1656-1658 ◽  
Author(s):  
Yu. N. Erokhin ◽  
J. Ravi ◽  
G. A. Rozgonyi ◽  
C. W. White
Keyword(s):  
Electric Field ◽  
Ion Implantation ◽  
Deep Trap

scholarly journals Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator

2019 ◽  
Vol 8 (12S2) ◽  
pp. 61-66
Keyword(s):  
Band Gap ◽  
Mole Fraction ◽  
High Performance ◽  
Device Simulation ◽  
Channel Length ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Simulation Results ◽  
High Performance Application ◽  
Device Modelling

This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.

Rapid Thermal Anneaung of Arsenic-Phosphorus(N+-N-) Double-Diffused Shallow Junctions

1985 ◽  
Vol 52 ◽  
Author(s):  
D. L. Kwong ◽  
N. S. Alvi ◽  
Y. H. Ku ◽  
A. W. Cheung
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Experimental Results ◽  
Silicon Substrates ◽  
Electrical Characteristics ◽  
Shallow Junctions

ABSTRACTDouble-diffused shallow junctions have been formed by ion implantation of both phosphorus and arsenic ions into silicon substrates and rapid thermal annealing. Experimental results on defect removal, impurity activation and redistribution, effects of Si preamorphization, and electrical characteristics of Ti-silicided junctions are presented.

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