1200-V, 50-A, Silicon Carbide Vertical Junction Field Effect Transistors for Power Switching Applications

2008 ◽  
Vol 600-603 ◽  
pp. 1047-1050 ◽  
Author(s):  
Victor Veliadis ◽  
Ty McNutt ◽  
Megan McCoy ◽  
Harold Hearne ◽  
Gregory De Salvo ◽  
...  
Keyword(s):  
Voltage Drop ◽  
Field Effect Transistors ◽  
Ring Structure ◽  
Avalanche Breakdown ◽  
Guard Ring ◽  
Gate Bias ◽  
Drain Voltage ◽  
Power Switching ◽  
Gate Current ◽  
Voltage Limit

High-voltage normally-on VJFETs of 0.19 cm2 and 0.096 cm2 areas were manufactured in seven photolithographic levels with no epitaxial regrowth and a single ion implantation event. A self aligned guard ring structure provided edge termination. At a gate bias of -36 V the 0.096 cm2 VJFET blocks 1980 V, which corresponds to 91% of the 12 μm drift layer’s avalanche breakdown voltage limit. It outputs 25 A at a forward drain voltage drop of 2 V (368 A/cm2, 735 W/cm2) and a gate current of 4 mA. The specific on-resistance is 5.4 mΩ cm2. The 0.19 cm2 VJFET blocks 1200 V at a gate bias of -26 V. It outputs 54 A at a forward drain voltage drop of 2 V (378 A/cm2, 755 W/cm2) and a gate current of 12 mA, with a specific on-resistance of 5.6 mΩ cm2. The VJFETs demonstrated low gate-to-source leakage currents with sharp onsets of avalanche breakdown.

1.4kV Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2011 ◽  
Vol 679-680 ◽  
pp. 607-612 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Kazuto Takao ◽  
Masaru Furukawa ◽  
Makoto Mizukami ◽  
...  
Keyword(s):  
Room Temperature ◽  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Mos Capacitor ◽  
Time Dependent Dielectric Breakdown ◽  
Blocking Voltage ◽  
Switching Characteristics

1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.

5 kV, 9.5 A SiC JBS Diodes with Non-Uniform Guard Ring Edge Termination for High Power Switching Application

2008 ◽  
Vol 600-603 ◽  
pp. 947-950 ◽  
Author(s):  
Jun Hu ◽  
Larry X. Li ◽  
Petre Alexandrov ◽  
Xiao Hui Wang ◽  
Jian Hui Zhao
Keyword(s):  
Energy Loss ◽  
High Power ◽  
Voltage Drop ◽  
Guard Ring ◽  
Power Switching ◽  
Edge Termination ◽  
Forward Current ◽  
Blocking Voltage ◽  
Bus Voltage ◽  
Ac Induction Motor

4H-SiC Junction Barrier Diodes (JBS) diodes were designed, fabricated and tested. The JBS diodes based on a 45μm thick, 1.4×1015cm-3 doped drift layer with multiple non-uniform spacing guard ring edge termination showed a blocking voltage of over 5kV. The 5kV JBS diode has a forward current density of 108A/cm2 at 3.5V and a specific on resistance (RSP_ON) of 25.2mW·cm2, which is very close to the theoretical RSP_ON of 23.3mΩ·cm2. DC I-V measurement of packaged JBS diodes showed a forward current of 100A at a voltage drop of 4.3V. A half-bridge inverter with a bus voltage up to 2.5kV was used to characterize the high power switching performance of SiC JBS diodes. A large inductance load of 1mH was used to simulate the load of a high power AC induction motor. Compared to a Si PIN diode module, the SiC JBS package reduces diode turn-off energy loss by 30% and Si IGBT turn-on energy loss by 21% at room temperature.

scholarly journals Gate Current and Snapback of 4H-SiC Thyristors on N+ Substrate for Power-Switching Applications

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 332
Author(s):  
Hojun Lee ◽  
Ogyun Seok ◽  
Taeeun Kim ◽  
Min-Woo Ha
Keyword(s):  
Numerical Simulation ◽  
Breakdown Voltage ◽  
Doping Concentration ◽  
Voltage Drop ◽  
Depletion Region ◽  
Drift Region ◽  
Power Switching ◽  
Gate Current ◽  
High Voltage Direct Current ◽  
Forward Voltage Drop

High-power switching applications, such as thyristor valves in a high-voltage direct current converter, can use 4H-SiC. The numerical simulation of the 4H-SiC devices requires specialized models and parameters. Here, we present a numerical simulation of the 4H-SiC thyristor on an N+ substrate gate current during the turn-on process. The base-emitter current of the PNP bipolar junction transistor (BJT) flow by adjusting the gate potential. This current eventually activated a regenerative action of the thyristor. The increase of the gate current from P+ anode to N+ gate also decreased the snapback voltage and forward voltage drop (Vf). When the doping concentration of the P-drift region increased, Vf decreased due to the reduced resistance of a low P-drift doping. An increase in the P buffer doping concentration increased Vf owing to enhanced recombination at the base of the NPN BJT. There is a tradeoff between the breakdown voltage and forward characteristics. The breakdown voltage is increased with a decrease in concentration, and an increase in drift layer thickness occurs due to the extended depletion region and reduced peak electric field.

1360 V, 5.0 mΩcm2 Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2010 ◽  
Vol 645-648 ◽  
pp. 987-990 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Makoto Mizukami ◽  
Chiharu Ota ◽  
Shinsuke Harada ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Blocking Voltage

Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

14.6 mΩcm2 3.3 kV DIMOSFET on 4H-SiC (000-1)

2014 ◽  
Vol 778-780 ◽  
pp. 935-938 ◽  
Author(s):  
Hiroshi Kono ◽  
Masaru Furukawa ◽  
Keiko Ariyoshi ◽  
Takuma Suzuki ◽  
Yasunori Tanaka ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Current Spread ◽  
Blocking Voltage

Silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The effect of current spread layer (CSL) structure was studied. 1.9 mm × 1.9 mm DIMOSFETs were characterized from room temperature to 200°C. At room temperature, the specific on-resistance of this MOSFET was 14.8 mΩcm2 at a gate bias of 20 V and a drain voltage of 0.5 V. The blocking voltage of this MOSFET was 3300 V. At 300 °C, the specific on-resistance increased from 14.8 mΩcm2 to 83.9 mΩcm2 and the threshold voltage decreased from 5.3 V to 3.4 V.

Erratum: High-gain GaInP/GaAs heterojunction phototransistor utilising guard-ring structure

1989 ◽  
Vol 25 (4) ◽  
pp. 296
Author(s):  
J.K. Twynam ◽  
P.A. Claxton ◽  
R.C. Woods ◽  
D.R. Wight
Keyword(s):  
High Gain ◽  
Ring Structure ◽  
Guard Ring

scholarly journals Evaluation of VTH and RON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 441
Author(s):  
Marcello Cioni ◽  
Alessandro Bertacchini ◽  
Alessandro Mucci ◽  
Nicolò Zagni ◽  
Giovanni Verzellesi ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Driving Voltage ◽  
Drain Voltage ◽  
Current Increase ◽  
Mode Operation ◽  
Switch Mode ◽  
Gate Signal ◽  
A Current ◽  
Parameter Monitoring

In this paper, we investigate the evolution of threshold voltage (VTH) and on-resistance (RON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative VTH shifts (i.e., VTH decrease) and negative RON drifts (i.e., RON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (VGH) and (ii) off-state drain voltage (VPH). We found that VTH reduction leads to a current increase, thus yielding RON to decrease. This correlation was explained by the RON dependence on the overdrive voltage (VGS–VTH). We also found that gate-related effects dominate the parameter drifts at low VPH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high VPH are completely recoverable within 1000 s from the VPH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed VTH and RON drifts.

Development of 1200 V, 3.7 mΩ-cm2 4H-SiC DMOSFETs for Advanced Power Applications

2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
Drain Current ◽  
Subthreshold Swing ◽  
Active Area ◽  
Gate Bias ◽  
Forward Voltage ◽  
Recent Developments ◽  
Forward Voltage Drop

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

scholarly journals 2D-Hydrodynamic Energy Model Including Avalanche Breakdown Phenomenon for Power Field Effect Transistors

VLSI Design ◽  
2001 ◽  
Vol 13 (1-4) ◽  
pp. 323-328
Author(s):  
M. Rousseau ◽  
J. C. De Jaeger
Keyword(s):  
Field Effect ◽  
Microwave Field ◽  
Field Effect Transistors ◽  
Computing Time ◽  
Avalanche Breakdown ◽  
Conservation Equations ◽  
Power Transistors ◽  
Breakdown Phenomenon ◽  
Gate Recess ◽  
Hydrodynamic Energy

A 2D-Hydrodynamic model is carried out to predict the breakdown voltage of microwave field effect transistors. The model is based on the conservation equations inferred from Boltzmann's transport equation, coupled with Poisson’s equation. In order to take into account the channel avalanche breakdown, the charge conservation equations for electrons and holes are considered and a generation term is introduced. The set of equations is solved using finite difference and different computational methods have been tested to save computing time. The model allows us to obtain accurate predictions for power transistors considering a usual gate recess. Results are performed for pseudomorphic ALGaAs/InGaAs/GaAs HEMTs.

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