Thin PSG Process for 4H-SiC MOSFET

2014 ◽  
Vol 778-780 ◽  
pp. 513-516 ◽  
Author(s):  
Yogesh K. Sharma ◽  
Ayayi C. Ahyi ◽  
Tamara Isaacs-Smith ◽  
Aaron Modic ◽  
Yi Xu ◽  
...  

The use of phosphorous as a passivating agent for the SiO2/4H-SiC interface increases the field effect channel mobility of 4H-SiC MOSFET to twice the value, 30-40cm2/V-s, that is obtained with a high temperature anneal in nitric oxide (NO). A solid SiP2O7planar diffusion source is used to produce P2O5for the passivation of the interface. Incorporation of phosphorous into SiO2leads to formation of phosphosilicate glass (PSG) which is known to be a polar material causes device instability. With a new modified thin phosphorous (P) passivation process, as described in this abstract, we can improve the stability of MOSFETs significantly with mobility around 75cm2/V.s.

2016 ◽  
Vol 858 ◽  
pp. 671-676 ◽  
Author(s):  
Daniel J. Lichtenwalner ◽  
Vipindas Pala ◽  
Brett A. Hull ◽  
Scott Allen ◽  
John W. Palmour

Alkaline earth elements Sr and Ba provide SiO2/SiC interface conditions suitable for obtaining high channel mobility metal-oxide-semiconductor field-effect-transistors (MOSFETs) on the Si-face (0001) of 4H-SiC, without the standard nitric oxide (NO) anneal. The alkaline earth elements Sr and Ba located at/near the SiO2/SiC interface result in field-effect mobility (μFE) values as high as 65 and 110 cm2/V.s, respectively, on 5×1015 cm-3 Al-doped p-type SiC. As the SiC doping increases, peak mobility decreases as expected, but the peak mobility remains higher for Ba interface layer (Ba IL) devices compared to NO annealed devices. The Ba IL MOSFET field-effect mobility decreases as the temperature is increased to 150 °C, as expected when mobility is phonon-scattering-limited, not interface-trap-limited. This is in agreement with measurements of the interface state density (DIT) using the high-low C-V technique, indicating that the Ba IL results in lower DIT than that of samples with nitric oxide passivation. Vertical power MOSFET (DMOSFET) devices (1200V, 15A) fabricated with the Ba IL have a 15% lower on-resistance compared to devices with NO passivation. The DMOSFET devices with a Ba IL maintain a stable threshold voltage under NBTI stress conditions of-15V gate bias stress, at 150 °C for 100hrs, indicating no mobile ions. Secondary-ion mass-spectrometry (SIMS) analysis confirms that the Sr and Ba remain predominantly at the SiO2/SiC interface, even after high temperature oxide annealing, consistent with the observed high channel mobility after these anneals. The alkaline earth elements result in enhanced SiC oxidation rate, and the resulting gate oxide breakdown strength is slightly reduced compared to NO annealed thermal oxides on SiC.


2014 ◽  
Vol 806 ◽  
pp. 139-142 ◽  
Author(s):  
Yogesh K. Sharma ◽  
A.C. Ahyi ◽  
Tamara Issacs-Smith ◽  
M.R. Jennings ◽  
S.M. Thomas ◽  
...  

The NO (nitric oxide) passivation process for 4H-SiC MOSFETs (silicon carbide metal-oxide-semiconductor filed effect transistors) effectively reduces the interface trap density and increases the inversion channel mobility from less that 10 to around 35cm2/V.s, only 5% of the bulk mobility. Recent results on the phosphorous passivation of the SiO2/4H-SiC interface have shown that it improves the mobility to about 90 cm2/V.s. Phosphorous passivation converts oxide (SiO2) into phosphosilicate glass (PSG) which is a polar material and results in device instabilities under abias-temperature stress (BTS) measurements. To limit the polarization effect, a new thin PSG process has been developed. The interface trap density of 4H-SiC-MOS capacitors using this process is as low as 3x1011cm-2eV-1. BTS results on MOSFETs have shown that the thin PSG devices are as stable as NO passivated devices with mobility around 80 cm2/V.s.


2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000219-000222
Author(s):  
F. Li ◽  
P.M. Gammon ◽  
C.W. Chan ◽  
F. Gity ◽  
T. Trajkovic ◽  
...  

Abstract Power Si/SiC LDMOSFET are being developed for the benefits of high temperature space and terrestrial harsh-environment applications. For the first time, high voltage devices are fabricated on a direct bonded Si/SiC substrate and characterised at room temperature. Peak field-effect channel mobility of the fabricated MOSFET reached ≈300 cm2/V.s and the avalanche breakdown was not observed up to 200 V, despite of a high leakage current in the device off-mode.


2016 ◽  
Vol 858 ◽  
pp. 623-626 ◽  
Author(s):  
Hua Rong ◽  
Yogesh K. Sharma ◽  
Tian Xiang Dai ◽  
Fan Li ◽  
M.R. Jennings ◽  
...  

This paper presents and analyse the experimental results of 4H-SiC(0001) lateral MOSFETs and MOS capacitors with gate oxides grown directly in N2O environment or in O2 ambient followed by a N2O post oxidation annealing process. Different nitridation temperatures of 1200°C, 1300°C, 1400°C and 1500°C have been investigated. Results have demonstrated that at high temperature (>1200°C) there is a significant improvement in the interface trap density (~1.5×1011 cm-2eV-1 at 0.2 eV) and field effect channel mobility (19 cm2/V.s) of 4H-SiC MOSFET compare with those at lower temperature (1×1012 cm-2eV-1 at 0.2 eV and 4 cm2/V.s). Among those nitridation temperatures, 1300°C has found to be the most effective in increasing the field effect channel mobility and reducing threshold voltage.


2001 ◽  
Vol 22 (4) ◽  
pp. 176-178 ◽  
Author(s):  
G.Y. Chung ◽  
C.C. Tin ◽  
J.R. Williams ◽  
K. McDonald ◽  
R.K. Chanana ◽  
...  

2016 ◽  
Vol 858 ◽  
pp. 639-642 ◽  
Author(s):  
Hidenori Kitai ◽  
Tomoaki Hatayama ◽  
Hideto Tamaso ◽  
Shinaya Kyogoku ◽  
Takeyoshi Masuda ◽  
...  

We have systematically investigated the trench properties of 4H-SiC for p-type channel doping level formed by epitaxial growth, crystallographic plane, and MOS interface treatment. Our results show that the channel mobilities on the (1-100), (11-20), (-1100), and (-1-120) planes gradually decreased in the range from 1 × 1016 to 1 × 1017 cm-3 as the epitaxial channel concentration increased. An inevitable tradeoff existed between channel mobility (field-effect mobility, µFE) and threshold voltage (Vth) in trench MOSFETs. Furthermore, the maximum µFE at a channel concentration of 1 × 1017 cm-3 was 95 cm2·V-1·s-1 on the (11-20) plane with wet + hydrogen (H2) annealing, 83 cm2·V-1·s-1 on the (1-100) plane with wet + H2 annealing and 57 cm2·V-1·s-1 on the (1-100) plane with nitric oxide annealing.


Author(s):  
E. R. Kimmel ◽  
H. L. Anthony ◽  
W. Scheithauer

The strengthening effect at high temperature produced by a dispersed oxide phase in a metal matrix is seemingly dependent on at least two major contributors: oxide particle size and spatial distribution, and stability of the worked microstructure. These two are strongly interrelated. The stability of the microstructure is produced by polygonization of the worked structure forming low angle cell boundaries which become anchored by the dispersed oxide particles. The effect of the particles on strength is therefore twofold, in that they stabilize the worked microstructure and also hinder dislocation motion during loading.


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