3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide

2011 ◽  
Vol 679-680 ◽  
pp. 645-648 ◽  
Author(s):  
Motoki Kobayashi ◽  
Hidetsugu Uchida ◽  
Akiyuki Minami ◽  
Toyokazu Sakata ◽  
Romain Esteve ◽  
...  
Keyword(s):  
Titanium Nitride ◽  
High Performance ◽  
Room Temperature ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Mobility ◽  
Thermally Grown Oxides ◽  
Metal Gates ◽  
Blocking Voltage ◽  
Gate Oxide Integrity

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

Gate Oxide Reliability of 4H-SiC V-Groove Trench MOSFET with Thick Bottom Oxide

2015 ◽  
Vol 821-823 ◽  
pp. 741-744
Author(s):  
Toru Hiyoshi ◽  
Takeyoshi Masuda ◽  
Yu Saitoh ◽  
Keiji Wada ◽  
Takashi Tsuno ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Oxide ◽  
The Novel ◽  
Constant Voltage ◽  
Channel Mobility ◽  
Oxide Reliability ◽  
Blocking Voltage ◽  
Voltage Stress ◽  
The Stability

The authors reported the DMOSFETs fabricated on the 4H-SiC(0-33-8) in ECSCRM2012 and the novel V-groove MOSFETs, having (0-33-8) on the trench sidewall in ICSCRM2013. In this paper, we applied both the thick bottom oxide and the buried p+ regions to the V-groove MOSFETs for the protection of the trench bottom oxide. The V-groove MOSFET showed the low specific on-resistance of 3.2 mΩcm2 and the high blocking voltage of 1700 V on the bounty of the high channel mobility and the gate oxide protection, respectively. We also tested the gate oxide reliability of the V-groove MOSFET by constant-voltage stress TDDB measurement. The charge-to-breakdown was 18.0 C/cm2 at room temperature and 4.4 C/cm2 at 145°C. In addition, the stability of the threshold voltage was characterized with the VMOSFETs.

scholarly journals Study and Assessment of Defect and Trap Effects on the Current Capabilities of a 4H-SiC-Based Power MOSFET

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 735
Author(s):  
Fortunato Pezzimenti ◽  
Hichem Bencherif ◽  
Giuseppe De Martino ◽  
Lakhdar Dehimi ◽  
Riccardo Carotenuto ◽  
...  
Keyword(s):  
Drain Current ◽  
Oxide Semiconductor ◽  
Temperature Dependent ◽  
Channel Mobility ◽  
Blocking Voltage ◽  
Current Voltage ◽  
Wide Range ◽  
Temperature Ranges ◽  
Joint Contribution ◽  
State Resistance

A numerical simulation study accounting for trap and defect effects on the current-voltage characteristics of a 4H-SiC-based power metal-oxide-semiconductor field effect transistor (MOSFET) is performed in a wide range of temperatures and bias conditions. In particular, the most penalizing native defects in the starting substrate (i.e., EH6/7 and Z1/2) as well as the fixed oxide trap concentration and the density of states (DoS) at the 4H-SiC/SiO2 interface are carefully taken into account. The temperature-dependent physics of the interface traps are considered in detail. Scattering phenomena related to the joint contribution of defects and traps shift the MOSFET threshold voltage, reduce the channel mobility, and penalize the device current capabilities. However, while the MOSFET on-state resistance (RON) tends to increase with scattering centers, the sensitivity of the drain current to the temperature decreases especially when the device is operating at a high gate voltage (VGS). Assuming the temperature ranges from 300 K to 573 K, RON is about 2.5 MΩ·µm2 for VGS > 16 V with a percentage variation ΔRON lower than 20%. The device is rated to perform a blocking voltage of 650 V.

Design and Process Issues for Silicon Carbide Power DiMOSFETS

2000 ◽  
Vol 640 ◽  
Author(s):  
Sei-Hyung Ryu ◽  
Anant K. Agarwal ◽  
Nelson S. Saks ◽  
Mrinal K. Das ◽  
Lori A. Lipkin ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Structure ◽  
Channel Mobility ◽  
Power Mosfets ◽  
Buried Channel ◽  
P Type ◽  
Very High ◽  
Effective Channel

ABSTRACTThis paper discusses the design and process issues of high voltage power DiMOSFETs (Double implanted MOSFETs) in 4H-silicon carbide (SiC). Since Critical Field (EC) in 4H-SiC is very high (10X higher than that of a Si), special care is needed to protect the gate oxide. 2D device simulation tool was used to determine the optimal JFET gap, which provides adequate gate oxide protection as well as a reasonable JFET resistance. The other issue in 4H-SiC DiMOSFETs is extremely low effective channel mobility (μeff) in the implanted p-well regions. NO anneal of the gate oxide and buried channel structure are used for increasing μeff. NO anneal, which was reported to be very effective in increasing the μeff of SiC MOSFETS in p-type epilayers, did not produce reasonable μeff of SiC MOSFETs in the implanted p-well. Buried channel (BC) structure with 2.7×1012 cm−2 charge in the channel showed high μeff utilizing bulk buried channel, but resulted in a normally-on device. However, it was shown that by controlling the charge in the BC layer, a normally off device with high μeff can be produced. A 3.3 mm × 3.3 mm DiMOSFET with BC structure showed a drain current of 10 A, which is the highest current reported in SiC power MOSFETs to date, at a forward drop of 4.4 V with a gate bias of only 2.5 V.

4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal

2006 ◽  
Vol 527-529 ◽  
pp. 1265-1268 ◽  
Author(s):  
Jeffery B. Fedison ◽  
Chris S. Cowen ◽  
Jerome L. Garrett ◽  
E.T. Downey ◽  
James W. Kretchmer ◽  
...  
Keyword(s):  
Atomic Force Microscopy ◽  
High Temperature ◽  
Room Temperature ◽  
Gate Oxide ◽  
Surface Roughening ◽  
Force Microscopy ◽  
Atomic Force ◽  
N Source ◽  
High Temperature Anneal ◽  
Blocking Voltage

Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).

Improved Channel Mobility by Oxide Nitridation for N-Channel MOSFET on 3C-SiC(100)/Si

2016 ◽  
Vol 858 ◽  
pp. 667-670 ◽  
Author(s):  
Fan Li ◽  
Yogesh K. Sharma ◽  
M.R. Jennings ◽  
A. Pérez-Tomás ◽  
Vishal Ajit Shah ◽  
...  
Keyword(s):  
High Temperature ◽  
Room Temperature ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Oxidation Temperature ◽  
Channel Mobility ◽  
Si Substrates ◽  
Nitridation Process ◽  
Long Channel

In this work we studied the gate oxidation temperature and nitridation influences on the resultant 3C-SiC MOSFET forward characteristics. Conventional long channel lateral MOSFETs were fabricated on 3C-SiC(100) epilayers grown on Si substrates using five different oxidation process. Both room temperature and high temperature (up to 500K) forward IV performance were characterised, and channel mobility as high as 90cm2/V.s was obtained for devices with nitrided gate oxide, considerable higher than the ones without nitridation process (~70 cm2/V.s).

The Characteristics of MOSFETs Fabricated on the Trench Sidewalls of Various Faces Using 4H-SiC (11-20) Substrates

2006 ◽  
Vol 527-529 ◽  
pp. 1297-1300
Author(s):  
Hiroyuki Fujisawa ◽  
Takashi Tsuji ◽  
Masaharu Nishiura
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Channel Mobility ◽  
Effective Channel

This paper reports the channel mobilities of MOSFETs formed on the trench sidewalls with different crystal faces including (0001), (000-1), (1-100) and (0-33-8) using 4H-SiC (11-20) substrates. Deposited poly-Si was oxidized in wet ambient to form the gate oxide, and annealed in N2O (10%) ambient. The order of drain current of trench sidewall MOSFETs was (0-33-8) > (1-100) > (000-1) = (0001). We could gain comparatively high channel mobility on the (0-33-8) face. The maximum effective channel mobility (μeff) was 35cm2/Vs, and μeff at 2.5MV/cm was 29 cm2/Vs on the (0-33-8) face.

9 kV 4H-SiC IGBTs with 88 mΩ·cm2 of R diff, on

2007 ◽  
Vol 556-557 ◽  
pp. 771-774 ◽  
Author(s):  
Qing Chun Jon Zhang ◽  
Charlotte Jonas ◽  
Bradley Heath ◽  
Mrinal K. Das ◽  
Sei Hyung Ryu ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
High Power ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
Gate Bias ◽  
Channel Mobility ◽  
Fast Switching ◽  
Blocking Voltage ◽  
First Time

SiC IGBTs are suitable for high power, high temperature applications. For the first time, the design and fabrication of 9 kV planar p-IGBTs on 4H-SiC are reported in this paper. A differential on-resistance of ~ 88 m(cm2 at a gate bias of –20 V is achieved at 25°C, and decreases to ~24.8 m(cm2 at 200°C. The device exhibits a blocking voltage of 9 kV with a leakage current density of 0.1 mA/cm2. The hole channel mobility is 6.5 cm2/V-s at room temperature with a threshold voltage of –6.5 V resulting in enhanced conduction capability. Inductive switching tests have shown that IGBTs feature fast switching capability at both room and elevated temperatures.

Investigation of Oxide Films Prepared by Direct Oxidation of C-Face 4H-SiC in Nitric Oxide

2010 ◽  
Vol 645-648 ◽  
pp. 515-518 ◽  
Author(s):  
Dai Okamoto ◽  
Hiroshi Yano ◽  
Yuki Oshiro ◽  
Tomoaki Hatayama ◽  
Yukiharu Uraoka ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Direct Oxidation ◽  
Mos Capacitors

Characteristics of metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated by direct oxidation of C-face 4H-SiC in NO were investigated. It was found that nitridation of the C-face 4H-SiC MOS interface generates near-interface traps (NITs) in the oxide. These traps capture channel mobile electrons and degrade the performance of MOSFETs. The NITs can be reduced by unloading the samples at room temperature after oxidation. It is important to reduce not only the interface states but also the NITs to fabricate high-performance C-face 4H-SiC MOSFETs with nitrided gate oxide.

1360 V, 5.0 mΩcm2 Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2010 ◽  
Vol 645-648 ◽  
pp. 987-990 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Makoto Mizukami ◽  
Chiharu Ota ◽  
Shinsuke Harada ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Blocking Voltage

Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

Comparison of the Threshold-Voltage Stability of SiC MOSFETs with Thermally Grown and Deposited Gate Oxides

2010 ◽  
Vol 645-648 ◽  
pp. 681-684 ◽  
Author(s):  
Michael Grieb ◽  
Masato Noborio ◽  
Dethard Peters ◽  
Anton J. Bauer ◽  
Peter Friedrichs ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Drain Current ◽  
Gate Oxide ◽  
Electrical Characteristics ◽  
Gate Oxides ◽  
Operation Conditions ◽  
Mos Devices ◽  
Thermal Oxide ◽  
Order Of Magnitude

The electrical characteristics and the reliability of different oxides on the 4H-SiC Si-face for gate oxide application in MOS devices are compared under MOSFET operation conditions at room temperature, at 100°C and at 130°C. The oxides are either an 80nm thick deposited oxide annealed in NO or an 80nm thick grown oxide in diluted N2O. The deposited oxide shows significant higher QBD- and lower Dit-values as well as a stronger decrease of drain current under stress than the grown oxide. Although for the deposited oxide, the leakage current below subthreshold increases more than one order of magnitude during constant circuit stress at room temperature, for the thermal oxide it is quite constant, but at higher level for higher temperatures.

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