Electrical Characterisation of Thick 3C-SiC Layers Grown on Off-Axis 4H-SiC Substrates
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300 μm thick 3C-SiC epilayer was grown on off-axis 4H-SiC(0001) substrate with a high growth rate of 1 mm/hour. Dry oxidation, wet oxidation and N2O anneal were applied to fabricate lateral MOS capacitors on these 3C-SiC layers. MOS interface obtained by N2O anneal has the lowest interface trap density of 3~4x1011 eV-1cm-2. Although all MOS capacitors still have positive net charges at the MOS interface, the wet oxidised sample has the lowest effective charge density of ~9.17x1011 cm-2.
2013 ◽
Vol 740-742
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pp. 323-326
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2020 ◽
Vol 22
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pp. 100816
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2013 ◽
Vol 405
(29)
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pp. 9365-9374
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2015 ◽
Vol 269
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pp. 74-82
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2008 ◽
Vol 600-603
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pp. 115-118
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High growth-rate atomic layer deposition process of cerium oxide thin film for solid oxide fuel cell
2019 ◽
Vol 45
(3)
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pp. 3811-3815
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