Characterization of Circuit Blocks for Configurable Analog-Front-End

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000146-000153 ◽  
Author(s):  
Bruce W. Ohme ◽  
Mark R. Larson ◽  
Bhal Tulpule ◽  
Alireza Behbahani
Keyword(s):  
Embedded Systems ◽  
Integrated Circuit ◽  
Extreme Temperature ◽  
Silicon On Insulator ◽  
Instrumentation Amplifier ◽  
Signal Conditioning ◽  
Wafer Level ◽  
Voltage Range ◽  
Front End ◽  
Programmable Gain

Analog functions have been implemented in a Silicon-on-Insulator (SOI) process optimized for high-temperature (>225°C) operation. These include a linear regulator/reference block that supports input voltages up to 50V and provides multiple independent voltage outputs. Additional blocks provide configurable sensor excitation levels of up to 10V DC and/or 20V AC-differential, with current limiting and monitoring. A dual-channel Programmable-Gain-Instrumentation Amplifier (PGIA) and a high-level AC input block with programmable gain and offset serve signal conditioning, gain, and scaling needs. A multiplexer and analog buffer provide an output that is scaled and centered for down-stream A-to-D conversion. Limited component availability and high component counts deter development of sensing and control electronics for extreme temperature (>200°) applications. Systems require front-end power conditioning, sensor excitation and monitoring, response amplification, scaling, and multiplexing. Back-end Analog-to-Digital conversion and digital processing/control can be implemented using one or two integrated circuit chips, whereas the front-end functions require component counts in the dozens. The low level of integration in the available portfolio of SOI devices results in high component count when constructing signal conditioning interfaces for aerospace sensors. These include quasi-DC sensors such as thermo-couples, strain-gauges, bridge transducers as well as AC-coupled sensors and position transducers, such as Linear Variable Differential Transducers (LVDT's). Furthermore, a majority of sensor applications are best served by excitation/response voltage ranges that typically exceed the voltage range of digital electronics (either 5V or 3.3V in currently available digital IC's for use above 200°C). These constraints led Embedded Systems LLC to design a generic device which was implemented by Honeywell as an analog ASIC (Application Specific Integrated Circuit). This paper will describe the ASIC block-level capabilities in the context of the typical applications and present characterization data from wafer-level testing at the target temperature range (225C). This material is based upon work performed by Honeywell International under a subcontract from Embedded Systems LLC, funding for which was provided by the U.S. Air Force Small Business Innovative Research program.

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

A Floating-Gate-Based Four-Channel Reconfigurable Analog Front-End Integrated Circuit

2021 ◽  
Author(s):  
Zu-Jia Lo ◽  
Bipasha Nath ◽  
Yuan-Chuan Wang ◽  
Yun-Jie Huang ◽  
Hui-Chun Huang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Floating Gate ◽  
Front End ◽  
Analog Front End

scholarly journals Simultaneous Voltage and Current Measurement Instrumentation Amplifier for ECG and PPG Monitoring

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 679
Author(s):  
Jongpal Kim
Keyword(s):  
Integrated Circuit ◽  
Cardiovascular Health ◽  
Current Noise ◽  
Instrumentation Amplifier ◽  
Current Sensing ◽  
Application Specific Integrated Circuit ◽  
Time Division ◽  
Electrocardiogram Ecg ◽  
First Time ◽  
Application Specific

An instrumentation amplifier (IA) capable of sensing both voltage and current at the same time has been introduced and applied to electrocardiogram (ECG) and photoplethysmogram (PPG) measurements for cardiovascular health monitoring applications. The proposed IA can switch between the voltage and current sensing configurations in a time–division manner faster than the ECG and PPG bandwidths. The application-specific integrated circuit (ASIC) of the proposed circuit design was implemented using 180 nm CMOS fabrication technology. Input-referred voltage noise and current noise were measured as 3.9 µVrms and 172 pArms, respectively, and power consumption was measured as 34.9 µA. In the current sensing configuration, a current noise reduction technique is applied, which was confirmed to be a 25 times improvement over the previous version. Using a single IA, ECG and PPG can be monitored in the form of separated ECG and PPG signals. In addition, for the first time, a merged ECG/PPG signal is acquired, which has features of both ECG and PPG peaks.

An analog BiCMOS integrated circuit for front-end RDS decoder

1991 ◽  
Vol 37 (3) ◽  
pp. 585-591 ◽  
Author(s):  
A. Baschirotto ◽  
M. Cassis ◽  
P. Kirchlechner ◽  
F. Montecchi ◽  
G. Palmisano ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Front End

Design and characteristics of reflectivity tunable mirror with MZI and loop waveguide on SOI

2021 ◽  
Author(s):  
Yutaka Makihara ◽  
Moataz Eissa ◽  
Tomohiro AMEMIYA ◽  
Nobuhiko Nishiyama
Keyword(s):  
Phase Shift ◽  
Coupling Coefficient ◽  
Integrated Circuit ◽  
Silicon Photonics ◽  
Silicon On Insulator ◽  
Zehnder Interferometer ◽  
Directional Couplers ◽  
Photonic Integrated Circuit ◽  
Active Elements ◽  
Measurement Results

Abstract To achieve a reconfigurable photonic integrated circuit with active elements, we proposed a reflectivity tunable mirror constructed using a Mach–Zehnder interferometer (MZI) with a micro heater and loop waveguide on a silicon photonics platform. In this paper, the principle of the operation, design, fabrication, and measurement results of the mirror are presented. In theory, the phase shift dependence of the mirror relies on the coupling coefficient of the directional couplers of the MZI. When the coupling coefficient κ2 was 0.5 and 0.15, the reflection could be turned on and off with a phase shift of π/2 and π, respectively. The reflection power of the fabricated mirror on the silicon on insulator (SOI) substrate was changed by more than 20 dB by a phase shift. In addition, it was demonstrated that the phase shift dependence of the mirror changes with the coupling coefficient of the fabricated devices.

scholarly journals Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 553 ◽  
Author(s):  
Fikret Yildiz ◽  
Tadao Matsunaga ◽  
Yoichi Haga
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Ultrasonic Transducer ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Lateral Side ◽  
Membrane Thickness ◽  
Bonding Performance ◽  
Complex Admittance

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.

scholarly journals Backside Chippings Improvement through Wafer Dicing Parameter Optimization and Understanding the Anistropic Silicon Properties

2021 ◽  
pp. 144-152
Author(s):  
Aiza Marie E. Agudon ◽  
Bryan Christian S. Bacquian
Keyword(s):  
Integrated Circuit ◽  
Electronic Devices ◽  
Silicon Wafers ◽  
Form Complex ◽  
Work Related ◽  
Front End ◽  
Wafer Thickness ◽  
Fully Automatic ◽  
Direct Materials ◽  
Selection Of

Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing. Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips. Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects. The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.

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