Sensor Packaging: New Challenges for New Applications

2010 ◽  
Vol 2010 (1) ◽  
pp. 000687-000694
Author(s):  
Caroline Beelen-Hendrikx ◽  
Coen Tak
Keyword(s):  
Flip Chip ◽  
Flexible Substrate ◽  
Electrical Measurement ◽  
Ph Sensing ◽  
Molding Compound ◽  
Wire Bonds ◽  
The Wire ◽  
New Applications ◽  
Silicon Based ◽  
Electrical Connections

Advantages of silicon-based sensors are compatibility with CMOS, improved robustness and reliability, smaller size and reflow compatibility. Biosensors that use an electrical measurement principle need electrical connections and fluidic access to the die. This only works when the electrical interconnects are kept clean of biofluid and when the package is compatible with the biofluids, receptor chemicals and other sensor elements. In addition, the package needs to be very cheap. A simple plastic overmolded package with a hole in the compound at the sensor location is an effective solution. RFID sensors also need direct die access for gass and pH sensing. They require the integration of processor, memory, clock, battery and antenna. The package format depends on the application. For checking the quality of perishables during transport or in a store, a disposable flexible tag is needed whereas for smart building sensors, a plastic module is more appropriate. For the sensor tag, a flexible substrate and flip chip bare dies are used. Direct die access is realized by an opening in the flex. Battery and antenna are printed on the flex. Automotive sensors that are used under the hood need to cope with very high operating temperatures with peak temperatures of up to 200 °C and they need to be delamination free. The critical points in the standard plastic packages used today are the molding compound and the wire-bonds. Standard packages can be used up to 150 °C. For higher temperatures, the molding compound and the wire-bond interconnect are being improved.

Design and Fabrication of MEMS Based Microphone Module by Using 3D Chip-on-Chip Package

2007 ◽  
Author(s):  
Jeffery C. C. Lo ◽  
S. W. Ricky Lee
Keyword(s):  
Flip Chip ◽  
Lead Free Solder ◽  
Process Flow ◽  
Wire Bonds ◽  
Solder Bumps ◽  
Preliminary Study ◽  
Mems Device ◽  
Free Solder ◽  
On Chip ◽  
Electrical Connections

Packaging of the MEMS based microphone is very important as the sensing diaphragm is very fragile. A suitable packaging method is required for the MEMS based microphone. In order to have a better understanding of packaging related issues of microphone, commercially available MEMS based microphone package is studied. Based on the preliminary study, a 3D Chip-on-Chip modulus is selected. The detail process flow of the mentioned package will be discussed in the following sections. Flip chip with lead free solder bumps are used in the proposed 3D Chip-on-Chip modulus. In contrast, wire bonds are used in the commercial MEMS based microphone for electrical connections while die attached is used to provide the mechanical support. The advantages of using flip chip over wire bond in both manufacturability and reliability aspects are discussed. Several MEMS based microphone packaging related issues are studied and evaluated. The detail fabrication and assembly process flow will be presented. A prototype package with MEMS device is fabricated. It can be shown that the proposed 3D Chip-on-Chip modulus is feasible for packaging MEMS based microphone.

scholarly journals Predicting Fusing Current for Encapsulated Wire Bonds under Transient Loads

2010 ◽  
Vol 2010 (1) ◽  
pp. 000486-000493 ◽  
Author(s):  
Aditi Mallik ◽  
Roger Stout
Keyword(s):  
Single Pulse ◽  
Element Model ◽  
Current Response ◽  
Temperature Dependent ◽  
Wire Bonds ◽  
Potential Failure ◽  
Different Dimensions ◽  
Transient Loads ◽  
The Wire ◽  
Set Up

For high power IC chips, as device size inevitably decreases, the wire diameter unfortunately must decrease due to the need of finer pitch wires. Fusing or melting of wirebonds thus increasingly becomes one of the potential failure issues for such IC's. Experiments were performed under transient loads on dummy packages having aluminum, gold, or copper wires of different dimensions. A finite element model was constructed that correlates very well with the observed maximum operating currents for such wirebonds under actual experimental test conditions. A qualitative observation of typical current profiles, as fusing conditions were approached, was that current would reach a maximum value very early in the pulse, and then fall gradually. One goal achieved through the modeling was to show that the current in the wire falls with time due to the heating of the wire material. Correspondingly, the wire reaches the melting temperature not at the peak current but rather at the end of pulse. Further, modeling shows that knowledge of external resistance and inductance of the experimental set up are highly significant in determining the details of a fusing event, but if known along with the temperature-dependent wire properties, the simulation can predict the correct voltage and current response of the part with 2% error. On the other hand, lack of external circuit characteristics may lead to completely incorrect results. For instance, the assumption that current is constant until the wire heats to fusing temperature, or that current and temperature both rise monotonically to maximum values until the wire fuses, are almost certain to be wrong. The work has been carried out for single pulse events as well as pulse trains.

scholarly journals Analysis of a Fire Case Caused by Heat Generation due to Cu2O Breeding

2020 ◽  
Vol 34 (2) ◽  
pp. 54-63
Author(s):  
Jin-Young Park ◽  
Eui-Pyeong Lee
Keyword(s):  
Heat Generation ◽  
3D Ct ◽  
Fire Statistics ◽  
Eds Analysis ◽  
The Wire ◽  
Electrical Connections ◽  
Fire Origin

Although fires caused by heat generation due to Cu<sub>2</sub>O breeding in wire connections are well-known among fire investigators, there are few papers on the analysis and introduction of fire cases by heat generation due to Cu<sub>2</sub>O breeding. This study analyzed fire statistics caused by heat generation in electrical connections and the phenomena and features of heat generation due to Cu<sub>2</sub>O breeding. Then, a fire which occurred in the wire connection in a university lab by heat generation due to Cu<sub>2</sub>O breeding was analyzed in more detail. This fire case could reach a conclusion that heat generation due to Cu<sub>2</sub>O breeding caused a fire in the wire connection through the fire pattern investigation of fire origin, the visual investigation of wire connection, 3D CT, power-on-test, and stereoscopic microscopy, SEM and EDS analysis.

Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001963-001976
Author(s):  
Rabindra Das ◽  
Steven Rosser ◽  
Frank Egitto
Keyword(s):  
Flip Chip ◽  
New Technologies ◽  
High Reliability ◽  
Present Report ◽  
Flexible Substrate ◽  
System Level ◽  
Organic Substrates ◽  
Internal Layers ◽  
Microelectronics Packaging ◽  
Wide Range

The wide range of applications for medical electronics drives unique requirements that can differ significantly from commercial & military electronics. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. Advanced microelectronics packaging solutions with embedded passives are enabling SWaP reductions. Implementation of these solutions has realized up to 27X reduction in physical size for existing PWB assemblies, with significant reductions in weight. Shorter interconnects can also reduce or eliminate the need for termination resistors for some net topologies. Successful miniaturized products integrate the following design techniques and technologies: component footprint reduction, thin high density interconnects substrate technologies, I/O miniaturization and IC assembly capabilities. This paper presents fabrication and electrical characterization of embedded actives and passives on organic multilayered substrates. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on embedded chips, resistors, and capacitors. Embedded passive technology further enhances miniaturization by enabling components to be moved from the surface of the substrate to its internal layers. The use of thin film resistor material allows creating individual miniaturized buried resistors. These resistors provide additional length and width reduction with negligible increases to the overall substrate and module (SiP) height. Resistor values can vary from 5 ohm to 50 Kohm with tolerances from 5 to 20% and areas as small as 0.2 mm2. The embedded resistors can be laser trimmed to a tolerance of &lt;5% for applications that require tighter tolerance. The electrical properties of embedded capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide frequency and temperature range. A few test vehicles were assembled to do system level analysis. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch. In addition, new technologies for embedding a variety of active chips are being developed. A variety of active chips, including a chip having dimensions of one millimeter square, have been embedded and electrically connected to develop high performance packages.

Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)

2012 ◽  
Vol 2012 (1) ◽  
pp. 001137-001142 ◽  
Author(s):  
Ilyas Mohammed
Keyword(s):  
High Performance ◽  
Copper Interconnects ◽  
Free Standing ◽  
Positional Accuracy ◽  
Aspect Ratios ◽  
Fine Pitch ◽  
Wire Bonds ◽  
Solder Balls ◽  
The Wire ◽  
Interconnect Technology

For low power processors, stacking memory on top offers many advantages such as high performance due to memory-processor interface within package, small footprint and standard assembly. Package-on-package (PoP) is preferred method of stacking as it offers two discrete packages that are tested separately and can be sourced independently. However, current PoP interconnect technologies do not efficiently scale to meet the memory bandwidth requirements for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap, or using organic interposers are not practically achieving the high IO requirements, since the aspect ratios of these interconnects are limited. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology called Bond Via Array (BVA™) is presented that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. The three main challenges were forming free standing wire-bonds, molding the package while exposing the tips of the wire-bonds, and package stacking. The assembly results showed that the wire tips were within the desired positional accuracy and height, and the packages were stacked without any loss of yield. These results indicate that the BVA interconnect technology is promising for the very high density and fine pitch required for upcoming mobile computing systems.

Modeling Vibration Induced Fatigue Failure of Free Standing Wire Bonds

2017 ◽  
Vol 2017 (1) ◽  
pp. 000635-000640
Author(s):  
Zhenzhen Shen ◽  
James Storey ◽  
Otto Fanini ◽  
Michael Osterman
Keyword(s):  
Natural Frequency ◽  
Electronic Device ◽  
Experimental Testing ◽  
Preliminary Test ◽  
Time To Failure ◽  
Free Standing ◽  
Element Analysis ◽  
Molding Compound ◽  
Wire Bond ◽  
Wire Bonds

Abstract Wire bonds are used to connect device terminals to package terminals or substrate terminal that forms circuits that are needed to create desired higher level functions. If a wire bond breaks or becomes detached during operation, the desired function will be lost. Depending on the design, a loss in function could be catastrophic. Aluminum, gold, and copper wires are used to create wire bonds in electronic products. These materials have been selected for their ability to be formed as fine wires and their ability to provide low electrical resistance. In many electronics packages, wire bonds are encapsulated in a polymer molding compound that is used to protect the electronic device. However, in some electronic devices such as hermetically sealed cavity packages, wire bonds may be free-standing. Under vibration loading, free-standing wire bonds may be subject to failure due to mechanical fatigue. In this work, an analytic model is presented for predicting natural frequency of a free-standing wire bond and for assessing a wire bond time to failure under a harmonic loading condition. The model for natural frequency is calibrated by finite element analysis and validated through experimental testing. The life prediction model, a test plan, and preliminary test results are presented.

EFFECT OF BUMP HEIGHT ON THE RELIABILITY OF ACA FLIP CHIP JOINING WITH FR4 RIGID AND POLYIMIDE FLEXIBLE SUBSTRATE

1998 ◽  
Vol 08 (03n04) ◽  
pp. 217-224 ◽  
Author(s):  
ZONGHE LAI ◽  
RUOYIN LAI ◽  
KATRIN PERSSON ◽  
JOHAN LIU
Keyword(s):  
Flip Chip ◽  
Flexible Substrate ◽  
Bump Height

Optimizing System-on-Film (SOF) Design Using Finite Element Analysis

2011 ◽  
Author(s):  
Vikram Venkatadri ◽  
Mark Downey ◽  
Xiaojie Xue ◽  
Dipak Sengupta ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Flip Chip ◽  
Flexible Substrate ◽  
High Density ◽  
Design Solution ◽  
Design Parameters ◽  
Optimized Design ◽  
Element Analysis ◽  
Bonding Parameters

System-On-Film (SOF) module is a complex integration of a fine pitch high density die and surface mounted discrete devices on a polyimide (PI) film laminate. The die is connected to the film using a thermo-compression flip-chip bonding (TCB) process which is capable of providing a very high density interconnect at less than 50um pitch. Several design and bonding parameters have to be controlled in order to achieve a reliable bond between the Au bumps on the die and the Sn plated Cu traces on the PI film. In the current work, the TCB process is studied using Finite Element Analysis (FEA) to optimize the design parameters and assure proper process margins. The resultant forces acting on the bump-to-trace interfaces are quantified across the different potential geometrical combinations. Baseline simulations showed higher stresses on specific bump locations and stress gradients acting on the bumps along the different sides of the die. These observations were correlated to both the failures and near failures on the actual test vehicles. Further simulations were then utilized to optimize and navigate design tradeoffs at both the die and flexible substrate design levels for a more robust design solution. Construction analysis performed on parts built using optimized design parameters showed significant improvements and correlated well with the simulation results.

High Power LED Integrated With Silicon-Based Thermoelectric Cooler Package

2007 ◽  
Author(s):  
Ming-Ji Dai ◽  
Chih-Kuang Yu ◽  
Chun Kai Liu ◽  
Sheng-Liang Kuo
Keyword(s):  
High Power ◽  
Flip Chip ◽  
Light Emitting Diode ◽  
Infrared Camera ◽  
Junction Temperature ◽  
Integrating Sphere ◽  
Thermoelectric Cooler ◽  
High Power Led ◽  
Silicon Based ◽  
Light Efficiency

A new thermal management application of silicon-based thermoelectric (TE) cooler integrated with high power light emitting diode (LED) is investigated in present study. The silicon-based TE cooler herein is fabricated by MEMS fabrication technology and flip-chip assembly process that is used for high power LED cooling. An electrical-thermal conversion method is used to estimate the junction temperature of LED. Moreover, the Integrating Sphere is also used to measure the light efficiency of LED. The thermal images photographed by infrared camera demonstrated the cooling function of the silicon-based TE devices. The results also show that high power LED integrated with silicon-based thermoelectric cooler package can effectively reduce the thermal resistance to zero. In addition, the light efficiency of the LED (1W) will increase under low TE cooler input power (0.55W), which is about 1.3 times of that without TE cooler packaging.

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