Applicability of Existing Reliability Models: Focus on Finite Element Modeling of Various BGA Package Designs and Materials

2011 ◽  
Vol 2011 (1) ◽  
pp. 000223-000231
Author(s):  
Ali Fallah-Adl ◽  
Amaneh Tasooji ◽  
Ravi Mahajan ◽  
Nachiket Raravikar ◽  
Richard Harries ◽  
...  
Keyword(s):  
Finite Element ◽  
Flip Chip ◽  
Solder Joints ◽  
State University ◽  
Arizona State University ◽  
Element Analysis ◽  
Package Design ◽  
Reliability Models ◽  
Bga Package ◽  
Global And Local

The work presented here is one of the key elements of an integrated methodology for predicting reliability in packaging systems (IMPRPK) developed by Arizona State University (ASU) and Intel. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks: (1) Finite Element analysis (FEM) to predict loading conditions, (2) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, and (3) development of a probabilistic methodology to achieve an integrated reliability solution. The focus of this paper is on FEM (task 1), evaluating the effect of package design/form-factor and solder materials on the extent of deformation (e.g., inelastic stress/strain and strain energy density) experienced by BGA solder joints. Global and Local FEM results for two different package designs (Flip-chip and wire-bonded FLI) and two different BGA solder materials (lead-free SAC405 and lead-rich eutectic Sn37Pb) are discussed. The FEM results and the applicability of the existing reliability models (e.g., energy-based model) to the complex microelectronics packaging systems are validated through independent comparison with the accelerated thermal cycled (ATC) test data.

scholarly journals Prediction of Thermal Fatigue Life of Lead-Free BGA Solder Joints by Finite Element Analysis

2001 ◽  
Vol 42 (5) ◽  
pp. 809-813 ◽  
Author(s):  
Young-Eui Shin ◽  
Kyung-Woo Lee ◽  
Kyong-Ho Chang ◽  
Seung-Boo Jung ◽  
Jae Pil Jung
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Fatigue Life ◽  
Thermal Fatigue ◽  
Solder Joints ◽  
Lead Free ◽  
Element Analysis ◽  
Thermal Fatigue Life

Finite Element Analysis of Stress Singularities in Attached Flip Chip Packages

2000 ◽  
Vol 122 (4) ◽  
pp. 301-305 ◽  
Author(s):  
A. Q. Xu ◽  
H. F. Nied
Keyword(s):  
Contact Angle ◽  
Finite Element ◽  
Glass Fiber ◽  
Flip Chip ◽  
Three Dimensional ◽  
Stress Singularity ◽  
Local Stress ◽  
Stress Singularities ◽  
Element Analysis ◽  
Three Dimensional Finite Element

Cracking and delamination at the interfaces of different materials in plastic IC packages is a well-known failure mechanism. The investigation of local stress behavior, including characterization of stress singularities, is an important problem in predicting and preventing crack initiation and propagation. In this study, a three-dimensional finite element procedure is used to compute the strength of stress singularities at various three-dimensional corners in a typical Flip-Chip assembled Chip-on-Board (FCOB) package. It is found that the stress singularities at the three-dimensional corners are always more severe than those at the corresponding two-dimensional edges, which suggests that they are more likely to be the potential delamination sites. Furthermore, it is demonstrated that the stress singularity at the upper silicon die/epoxy fillet edge can be completely eliminated by an appropriate choice in geometry. A weak stress singularity at the FR4 board/epoxy edge is shown to exist, with a stronger singularity located at the internal die/epoxy corner. The influence of the epoxy contact angle and the FR4 glass fiber orientation on stress state is also investigated. A general result is that the strength of the stress singularity increases with increased epoxy contact angle. In addition, it is shown that the stress singularity effect can be minimized by choosing an appropriate orientation between the glass fiber in the FR4 board and the silicon die. Based on these results, several guidelines for minimizing edge stresses in IC packages are presented. [S1043-7398(00)00904-X]

A Non-Through Silicon Via 1000+ IO Package On Package Solution For Wide IO Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000094-000099 ◽  
Author(s):  
Laura Mirkarimi ◽  
Rajesh Katkar ◽  
Ron Zhang ◽  
Rey Co ◽  
Zhijun Zhao
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Design Optimization ◽  
High Yield ◽  
Element Analysis ◽  
Package Design ◽  
Simulation Methodology ◽  
Structural Modifications ◽  
Simulation Tools ◽  
Large Bandwidth

We are developing a new solution for wide I/O package on package applications, which is Bond Via Array (BVA) technology. The prototype vehicle built in this study has 1020 I/O's at a pitch of 0.24 mm with a high aspect ratio of approximately 10:1 and is ≤1.4 mm tall. PoP applications require large bandwidth and thinner packages challenging package developers to address warpage control for high yield processes. The design optimization of this package was established through rigorous finite element analysis of materials selection and structural modifications. The simulation methodology was validated by measuring the warpage as a function of temperature for the experimental prototypes. The details for the simulation and verification processes for the wide I/O process will be discussed. The variation between finite element analysis predictions and the experimental builds was ~10%, which allowed us to complete package design optimization with our simulation tools. The prototype build includes a standard and a low CTE substrate.

A Nonlinear and Time Dependent Finite Element Analysis of Solder Joints in Surface Mounted Components Under Thermal Cycling

1991 ◽  
Vol 226 ◽  
Author(s):  
Yi-Hsin Pao ◽  
Kuan-Luen Chen ◽  
An-Yu Kuo
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Thermal Cycling ◽  
Solder Joints ◽  
Free Edge ◽  
Time Dependent ◽  
Element Analysis ◽  
Finite Element Program ◽  
Element Program ◽  
Peel Stress

AbstractA nonlinear and time dependent finite element analysis was performed on two surface mounted electronic devices subjected to thermal cycling. Constitutive equations accounting for both plasticity and creep for 37Pb/63Sn and 90Pb/10Sn solders were assumed and implemented in a finite element program ABAQUS with the aid of a user subroutine. The FE results of 37Pb/63Sn solder joints were in reasonably good agreement with the experimental data by Hall [19]. In the case of 9OPb/1OSn solder in a multilayered transistor stack, the FE results showed the existence of strong peel stress near the free edge of the joint, in addition to the anticipated shear stress. The effect of such peel stress on the crack initiation and growth as a result of thermal cycling was discussed, together with the singular behavior of both shear and peel stresses near the free edge.

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