I/O Printed Circuit Board Assemblies; Recent Learning in Mechanical Stress Analysis, Verification Testing, and Post-test Analysis Techniques and Results

2015 ◽  
Vol 2015 (1) ◽  
pp. 000169-000178
Author(s):  
John Torok ◽  
Shawn Canfield ◽  
Suraush Khambati ◽  
Robert Mullady ◽  
Budy Notohardjono ◽  
...  

Recent high-end server designs have included new Input / Output (I/O) printed circuit board (PCB) assemblies consisting of a variety of form factors, electronic design layouts, and packaging assembly characteristics. To insure the required functional and reliability aspects are established and maintained, new mechanical analysis and verification testing techniques have been recently devised. A description of the design application set, the analysis tools and techniques applied, and the verification testing completed, including the associated measurement techniques as well as post-testing analysis methods and results are presented. Also included are the recent PCB raw card characterization efforts whose results have been applied as material property inputs to the analysis to improve analytical-to-empirical correlation. Included within the application set are both the use of custom designed cards as well as industry standard, original equipment manufacturer (OEM) cards that are packaged within custom enclosures. Given packaged and unpackaged (i.e., as installed in a higher-level rack system assembly) fragility testing requirements, new analysis techniques exploiting the capabilities of LS-DYNA have been used to provide a predictive means to support both initial as well as iterative design levels. In addition, these analysis results are also used to identify locations for measurement sensor placement employed during mechanical verification testing. Thermal shock and mechanical shock and vibration verification testing details and results are provided describing the conditions applied to simulate assembly shipping conditions, both as packaged as well as in situ to the higher-level of assembly. Included with this is a discussion with respect to post-test analysis techniques and results, including the use of both microscopic cross-section analysis as well as dye-pry assessments. Concluding, continued and future activities are described as “best practices” for the application of this methodology as part of the end-to-end development process.

2012 ◽  
Vol 226-228 ◽  
pp. 345-350
Author(s):  
Fei Xu ◽  
Chuan Ri Li ◽  
Tong Min Jiang ◽  
Long Tao Liu

Various failures in electronic systems, particularly in the connections between the printed circuit board (PCB) and components, are due to mechanical shock and vibration. The vibration characteristic of a plug-in PCB in an airborne electronic case (AEC) was studied first by finite element modeling (FEM) and experimental techniques. The coupling method and torsional spring elements were used in FEM to better simulate the PCB’s realistic boundary condition. A reasonable correlation between simulation and test results was obtained. Since the fundamental frequency is one of the most important dynamic characteristics of PCB, the orthogonal design and variance analysis, as well as FEM method, were discussed subsequently to investigate the effects of different factors. Analysis results demonstrate a good correlation with current studies. Finally, a general design guideline was presented to maximize the PCB’s fundamental frequency.


2021 ◽  
Vol 11 (6) ◽  
pp. 2679
Author(s):  
Andrew Wileman ◽  
Suresh Perinpanayagam ◽  
Sohaib Aslam

This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a life-cycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems.


2012 ◽  
Vol 132 (6) ◽  
pp. 404-410 ◽  
Author(s):  
Kenichi Nakayama ◽  
Kenichi Kagoshima ◽  
Shigeki Takeda

2014 ◽  
Vol 5 (1) ◽  
pp. 737-741
Author(s):  
Alejandro Dueñas Jiménez ◽  
Francisco Jiménez Hernández

Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the “speeds” on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were extracted from the chapter eight of book “2-D Electromagnetic Simulation of Passive Microstrip Circuits” from the corresponding author of this paper.


Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.


Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.


Author(s):  
Jun-Xian Fu ◽  
Shukri Souri ◽  
James S. Harris

Abstract Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.


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