scholarly journals A Novel Approach for Analysis CNTFET Based Domino circuit in Nano-Scale Design

2020 ◽  
Vol 14 ◽  
Keyword(s):  
Supply Voltage ◽  
Average Power ◽  
Process Technology ◽  
Novel Approach ◽  
Domino Circuit ◽  
Standby Power ◽  
Simulation Results ◽  
Scale Design ◽  
Domino Circuits ◽  
Day By Day

As semiconductor industries is developing day by day to meet the requirement of today’s world. As scaling of ICs day by day to introduce functionality of the device while fabrication more and more component which results in shorter the life of the battery operated device which has to be improved. Here in this article we have measured performance parameters like power consumption, UNG, Evaluation Delay, standby power and speed of various domino circuits provided for various inputs like 8 &16 input OR gate. When we compared power, delay, and PDP of different topologies of domino circuit design with the simulation results which is performed by using SPICE tool at 32nm CNTFET process technology with supply voltage 0.9V and 27⁰ C of temperature at 100 MHz. All the simulation results is done in CMOS & CNTFET technology, it is observed that saving of average power upto 90.46% with same delay, with improvement of 5.8 × Noise-immunity with scaling of technology.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

Steep-Slope Devices: Prospects and Challenges

2016 ◽  
Vol 39 ◽  
pp. 3-16 ◽  
Author(s):  
Elena Gnani ◽  
Emanuele Baravelli ◽  
Pasquale Maiorano ◽  
Antonio Gnudi ◽  
Susanna Reggiani ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Supply Voltage ◽  
Steep Slope ◽  
Oxide Interface ◽  
Novel Device ◽  
Tunnel Fet ◽  
Standby Power ◽  
Simulation Results ◽  
Low Performance

In this work, an overview is given on the prospects and challenges of two novel device concepts,namely the Tunnel FET (TFET) and the Superlattice FET (SL-FET). The optimization effort ofhomo- and hetero-junction TFETs carried out so far shows that these devices can provide an advantageover CMOS FETs only for very-low power and low-performance niche applications, so long asthe supply voltage is scaled below 300 mV. The required materials for homojunction TFETs are lowbandgap semiconductors, such as InAs and InGaAs; for heterojunction TFETs the best semiconductorpair appears to be (Al)GaSb-InAs. Several technological problems are still unsolved: poor qualityof the oxide interface with III-V materials and device variability are probably the most important. The SL-FET represents in principle a better device concept, as it provides outstanding performance and meets nearly all targets of the high performance (HP), low operating power (LOP) and low standby power (LSTP) of the ITRS at VDD = 0.4V. A suitably-designedInGaAs-InAlAs SL-FET has turned out to provide the best simulation results. However, the fabricationprocess of SL-FETs is much more complex, as it requires molecular epitaxy to deposit multiplelayers with a very strict control of their nanometric thickness. Besides, vertical devices can poseunexpected problems as far as layout organization and parasitics are concerned.

scholarly journals Design of voltage level shifter for power-efficient applications using 45nm technology

2018 ◽  
Vol 7 (2.8) ◽  
pp. 103
Author(s):  
P Sahithi ◽  
K Hari Kishore ◽  
E Raghuveera ◽  
P Gopi Krishna
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Average Power ◽  
Current Mirror ◽  
Input Frequency ◽  
Voltage Level ◽  
Power Efficient ◽  
Voltage Range ◽  
Level Shifter ◽  
Simulation Results

The paper describes a voltage level shifter for power efficient applications which is simulated in tanner spice tool using 45nm technology. The conservative voltage level shifter is designed by using 6 transistors. The voltage level shifter cell generally used for shifting the voltage range of the signal from one voltage domain to another. This is required when the chip operate at multiple voltage domains. The circuit parameters like leakage voltage and average power dissipation are calculate for this circuit. Mainly level shifter consists of two voltage levels. One is low logic supply voltage (VDDL) another one is high logic supply voltage (VDDH). The simulation results of proposed level shifter with Wilson current mirror by 45nm technology for the input frequency of 1MHZ, the power dissipation of 0.177nW with 3db gain of 9.78.

A Novel Approach for PAPR Reduction of NC-OFDM System

2014 ◽  
Vol 519-520 ◽  
pp. 1021-1026
Author(s):  
Hui Fang
Keyword(s):  
Band System ◽  
Average Power ◽  
Matlab Simulation ◽  
Ofdm System ◽  
Authorized User ◽  
Novel Approach ◽  
Carrier Interferometry ◽  
Simulation Results ◽  
Base Band ◽  
Ber Performance

Although Non-continuous OFDM (NC-OFDM) has the unique advantage of eliminating interference to authorized user in cognitive radio context, it also confronts a difficulty of reducing peak to average power ratio (PAPR) like other OFDM techniques. In this paper, carrier interferometry is proposed to apply in NC-OFDM system in order to reduce its PAPR using the construction feature of CI code itself. The coding principle of CI code is analyzed at first. Then NC-OFDM base-band system based on carrier interferometry (CI/NC-OFDM) is modeled. Theoretical analysis and matlab simulation results indicate that CI code can bring 3 dB lower PAPR reference with the same probability of exceeding some PAPR reference, compared with traditional NC-OFDM system. This method is effective and feasible and gets better BER performance as well.

12-BIT PSEUDO-DIFFERENTIAL CURRENT-SOURCE RESISTOR-STRING HYBRID DAC

2011 ◽  
Vol 20 (04) ◽  
pp. 709-725 ◽  
Author(s):  
M. T. S. AB-AZIZ ◽  
A. MARZUKI ◽  
Z. A. A. AZIZ
Keyword(s):  
Supply Voltage ◽  
Current Source ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Process Technology ◽  
Analog Converter ◽  
Final Design ◽  
Resistor String ◽  
Simulation Results ◽  
Binary Weighted

This paper discusses a hybrid Digital-Analog Converter (DAC) architecture which is a combination of a binary-weighted resistor approach for eight bits in the least-significant-bit and thermometer coded approach for four bits in the most-significant-bit. The proposed design combines advantages of the binary-weighted resistor approach and thermometer coded approach. The final design is composed of two 12-bit DACs to achieve a pseudo differential output signal. The converter was designed with a Silterra 0.18 μm 1.8 V/3.3 V CMOS process technology. The post-layout simulation results show that this design achieves 12-bit resolution with INL and DNL of 0.375 LSB and 0.25 LSB, respectively. The power consumption is 6.291 mW when the designed DAC is biased with supply voltage equal to 3 V. The performance is accomplished with a design area of 230 μm × 255 μm.

scholarly journals HF-QSRAM: Half-Select Free Quaternary SRAM Design with Required Peripheral Circuits for IoT/IoVT Applications

2022 ◽  
Author(s):  
Arsalan Ghasemian ◽  
Ebrahim Abiri ◽  
Kourosh Hassanli ◽  
Abdolreza Darabi
Keyword(s):  
Monte Carlo ◽  
Storage Capacity ◽  
Supply Voltage ◽  
Average Power ◽  
Access Frequency ◽  
Average Power Consumption ◽  
Sram Design ◽  
Standby Power ◽  
Increasing Demand ◽  
Fabrication Parameters

Abstract By using CNFET technology in 3a 2 nm node using a proposed SQI gate, two split bit-lines QSRAM architectures have been suggested to address the issue of increasing demand for storage capacity in IoT/IoVT applications. Peripheral circuits such as a novel quaternary to binary decoder for QSRAM have been offered. Various simulations on temperature, supply voltage, and access frequency have been done to evaluate and ensure the performance of the proposed SQI gate, suggested cells, and quaternary to binary decoder. Moreover, 1000 Monte-Carlo analyses on the fabrication parameters have been done to classify read and write delay and standby power of proposed cells along with PDP of proposed quaternary to binary decoder. It is worth mentioning that the PDP of the proposed SQI gate, decoder, and average power consumption of suggested HF-QSRAM cell reached 0.92 aJ, 4.13 aJ, and 0.15 µW, respectively, which are approximately 80%, 91%, and 33% improvements in comparison with the best existing designs in the literature.

An Intuitionistic Fuzzy Based Novel Approach to CPU Scheduler

2020 ◽  
Vol 16 (4) ◽  
pp. 316-328
Author(s):  
Supriya Raheja
Keyword(s):  
Fuzzy Inference ◽  
The Other ◽  
Simulation Environment ◽  
Inference System ◽  
Intuitionistic Fuzzy ◽  
Novel Approach ◽  
Continuous Feedback ◽  
Simulation Results ◽  
Effectiveness And Efficiency ◽  
Unique Capability

Background: The extension of CPU schedulers with fuzzy has been ascertained better because of its unique capability of handling imprecise information. Though, other generalized forms of fuzzy can be used which can further extend the performance of the scheduler. Objectives: This paper introduces a novel approach to design an intuitionistic fuzzy inference system for CPU scheduler. Methods: The proposed inference system is implemented with a priority scheduler. The proposed scheduler has the ability to dynamically handle the impreciseness of both priority and estimated execution time. It also makes the system adaptive based on the continuous feedback. The proposed scheduler is also capable enough to schedule the tasks according to dynamically generated priority. To demonstrate the performance of proposed scheduler, a simulation environment has been implemented and the performance of proposed scheduler is compared with the other three baseline schedulers (conventional priority scheduler, fuzzy based priority scheduler and vague based priority scheduler). Results: Proposed scheduler is also compared with the shortest job first CPU scheduler as it is known to be an optimized solution for the schedulers. Conclusion: Simulation results prove the effectiveness and efficiency of intuitionistic fuzzy based priority scheduler. Moreover, it provides optimised results as its results are comparable to the results of shortest job first.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

A novel identification approach for shearer running status through integration of rough sets and improved wavelet neural network

2016 ◽  
Vol 230 (16) ◽  
pp. 2792-2805 ◽  
Author(s):  
Lei Si ◽  
Zhongbin Wang ◽  
Xinhua Liu
Keyword(s):  
Neural Network ◽  
Genetic Algorithm ◽  
Rough Sets ◽  
Particle Swarm Optimization Algorithm ◽  
Wavelet Neural Network ◽  
Decision Table ◽  
Swarm Optimization ◽  
Novel Approach ◽  
Identification Approach ◽  
Simulation Results

In order to accurately and conveniently identify the shearer running status, a novel approach based on the integration of rough sets (RS) and improved wavelet neural network (WNN) was proposed. The decision table of RS was discretized through genetic algorithm and the attribution reduction was realized by MIBARK algorithm to simply the samples of WNN. Furthermore, an improved particle swarm optimization algorithm was proposed to optimize the parameters of WNN and the flowchart of proposed approach was designed. Then, a simulation example was provided and some comparisons with other methods were carried out. The simulation results indicated that the proposed approach was feasible and outperforming others. Finally, an industrial application example of mining automation production was demonstrated to verify the effect of proposed system.

LOW POWER CONTINUOUS TIME COMMON MODE SENSING FOR COMMON MODE FEEDBACK CIRCUITS

2010 ◽  
Vol 19 (03) ◽  
pp. 519-528 ◽  
Author(s):  
M. PRAMOD ◽  
T. LAXMINIDHI
Keyword(s):  
Continuous Time ◽  
Input Impedance ◽  
Cmos Process ◽  
High Input ◽  
High Input Impedance ◽  
Common Mode ◽  
Standby Power ◽  
Low Distortion ◽  
Simulation Results ◽  
Feedback Circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.

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