Designing Software Configurable Chips and SIPs using Chiplets and zGlue

2019 ◽  
Vol 2019 (1) ◽  
pp. 000027-000032
Author(s):  
Jawad Nasrullah ◽  
Zhiquan Luo ◽  
Greg Taylor
Keyword(s):  
Rapid Development ◽  
Data Representation ◽  
Design Tool ◽  
Smart Devices ◽  
Wafer Level ◽  
Ic Design ◽  
Fine Pitch ◽  
Design Style ◽  
Cloud Users ◽  
Known Good Die

Abstract zGlue Smart Fabric, an active silicon interposer, enables rapid development of Systems in Package (SiPs) and Chips using chiplet stacking in a modular style and software programmability. zGlue Smart Fabric works with off-the-shelf chiplets in known good die and wafer level chip scale packages format without dictating a footprint constraint on chiplets. This is achieved by making a fine pitch copper pillar micro-bump array on the surface that can conform to the chiplet ball map using a programable connectivity and power array built into zGlue's fabric. Connection to RF and sensitive analog signals are handled in RDL. Programmability of zGlue bumps also enable some repair and reconfigurability after manufacturing. The design process with zGlue includes usage of a cloud-based software design tool called ChipBuilder. This tool performs most conventional SiP design functions but more importantly it is used for creating soft and hard routes among IOs. ChipBuilder starts with a data representation of zGlue's Smart Fabric. A growing library of chiplet data has been encoded into the tool and is made available to the users of ChipBuilder via the cloud. Users select chiplets, enter design, perform IO planning, and route the design. With this modular IC design style, zGlue can handle high mix devices that are expected with the growth of connected smart devices everywhere.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

scholarly journals Investigating the Temporal Effect of User Preferences with Application in Movie Recommendation

2017 ◽  
Vol 2017 ◽  
pp. 1-10 ◽  
Author(s):  
Wen-Jun Li ◽  
Qiang Dong ◽  
Yan Fu
Keyword(s):  
Rapid Development ◽  
User Preferences ◽  
Mobile Internet ◽  
Smart Devices ◽  
Data Sets ◽  
Rating Data ◽  
Temporal Effect ◽  
Proposed Model ◽  
Target User ◽  
The Difference

As the rapid development of mobile Internet and smart devices, more and more online content providers begin to collect the preferences of their customers through various apps on mobile devices. These preferences could be largely reflected by the ratings on the online items with explicit scores. Both of positive and negative ratings are helpful for recommender systems to provide relevant items to a target user. Based on the empirical analysis of three real-world movie-rating data sets, we observe that users’ rating criterions change over time, and past positive and negative ratings have different influences on users’ future preferences. Given this, we propose a recommendation model on a session-based temporal graph, considering the difference of long- and short-term preferences, and the different temporal effect of positive and negative ratings. The extensive experiment results validate the significant accuracy improvement of our proposed model compared with the state-of-the-art methods.

scholarly journals Use of Augmented Reality to Create an iOS App with Watson Studio

2021 ◽  
Vol 4 ◽  
pp. 98-100
Author(s):  
Semen Gorokhovskyi ◽  
Yelyzaveta Pyrohova
Keyword(s):  
Higher Education ◽  
Machine Learning ◽  
Augmented Reality ◽  
New Technologies ◽  
Higher Education Institutions ◽  
Rapid Development ◽  
Easy Access ◽  
Smart Devices ◽  
The Real ◽  
The World

With the rapid development of applications for mobile platforms, developers from around the world already understand the need to impress with new technologies and the creation of such applications, with which the consumer will plunge into the world of virtual or augmented reality. Some of the world’s most popular mobile operating systems, Android and iOS, already have some well-known tools to make it easier to work with the machine learning industry and augmented reality technology. However, it cannot be said that their use has already reached its peak, as these technologies are at the stage of active study and development. Every year the demand for mobile application developers increases, and therefore more questions arise as to how and from which side it is better to approach immersion in augmented reality and machine learning. From a tourist point of view, there are already many applications that, with the help of these technologies, will provide more information simply by pointing the camera at a specific object.Augmented Reality (AR) is a technology that allows you to see the real environment right in front of us with a digital complement superimposed on it. Thanks to Ivan Sutherland’s first display, created in 1968 under the name «Sword of Damocles», paved the way for the development of AR, which is still used today.Augmented reality can be divided into two forms: based on location and based on vision. Location-based reality provides a digital picture to the user when moving through a physical area thanks to a GPS-enabled device. With a story or information, you can learn more details about a particular location. If you use AR based on vision, certain user actions will only be performed when the camera is aimed at the target object.Thanks to advances in technology that are happening every day, easy access to smart devices can be seen as the main engine of AR technology. As the smartphone market continues to grow, consumers have the opportunity to use their devices to interact with all types of digital information. The experience of using a smartphone to combine the real and digital world is becoming more common. The success of AR applications in the last decade has been due to the proliferation and use of smartphones that have the capabilities needed to work with the application itself. If companies want to remain competitive in their field, it is advisable to consider work that will be related to AR.However, analyzing the market, one can see that there are no such applications for future entrants to higher education institutions. This means that anyone can bring a camera to the university building and learn important information. The UniApp application based on the existing Swift and Watson Studio technologies was developed to simplify obtaining information on higher education institutions.

scholarly journals Head-on-Pillow Defect Detection: X-Ray Inspection Limitations

2019 ◽  
Vol 16 (2) ◽  
pp. 91-102
Author(s):  
Lars Bruno ◽  
Benny Gustafson
Keyword(s):  
Solder Joints ◽  
Solder Paste ◽  
Wafer Level ◽  
Reflow Soldering ◽  
X Ray ◽  
Soldering Process ◽  
Irregular Shapes ◽  
Fine Pitch ◽  
Solder Balls ◽  
Ball Grid Array Packages

Abstract Both the number and the variants of ball grid array packages (BGAs) are tending to increase on network printed board assemblies with sizes ranging from a few millimeter die size wafer level packages with low ball count to large multidie system-in-package (SiP) BGAs with 60–70 mm side lengths and thousands of I/Os. One big challenge, especially for large BGAs, SiPs, and for thin fine-pitch BGA assemblies, is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process, and this may result in solder joints with irregular shapes, indicating poor or no coalescence between the added solder and the BGA balls. This defect is called head-on-pillow (HoP) and is a failure type that is difficult to determine. In this study, x-ray inspection was used as a first step to find deliberately induced HoP defects, followed by prying off of the BGAs to verify real HoP defects and the fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as potential HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.

Robust voice user interface for internet-of-things

2021 ◽  
pp. 1-16
Author(s):  
Abdelaziz A. Abdelhamid ◽  
Sultan R. Alotaibi
Keyword(s):  
Internet Of Things ◽  
Smart Home ◽  
Industrial Revolution ◽  
Rapid Development ◽  
Smart Devices ◽  
Voice User ◽  
Voice Interaction ◽  
Device Interaction ◽  
Computational Resources ◽  
Human Device

Internet of things (IoT) plays significant role in the fourth industrial revolution and attracts an increasing interest due to the rapid development of smart devices. IoT comprises factors of twofold. Firstly, a set of things (i.e., appliances, devices, vehicles, etc.) connected together via network. Secondly, human-device interaction to communicate with these things. Speech is the most natural methodology of interaction that can enrich user experience. In this paper, we propose a novel and effective approach for building customized voice interaction for controlling smart devices in IoT environments (i.e., Smart home). The proposed approach is based on extracting customized tiny decoding graph from a large graph constructed using weighted finite sates transducers. Experimental results showed that tiny decoding graphs are very efficient in terms of computational resources and recognition accuracy in clean and noisy conditions. To emphasize the effectiveness of the proposed approach, the standard Resources Management (RM1) dataset was employed and promising results were achieved when compared with four competitive approaches.

Microsensors, MEMS and NEMS Based Complex Adaptive Smart Devices and Systems

2001 ◽  
Author(s):  
Vijay K. Varadan
Keyword(s):  
Self Assembly ◽  
Communication Systems ◽  
Microelectromechanical Systems ◽  
System Level ◽  
Smart Devices ◽  
Mems Devices ◽  
Wafer Level ◽  
Sensors And Actuators ◽  
Complex Adaptive ◽  
Microelectronics Industry

Abstract The microelectronics industry has seen explosive growth during the last thirty years. Extremely large markets for logic and memory devices have driven the development of new materials, and technologies for the fabrication of even more complex devices with features sizes now down at the sub micron level. Recent interest has arisen in employing these materials, tools and technologies for the fabrication of miniature sensors and actuators and their integration with electronic circuits to produce smart devices and MicroElectroMechanical Systems (MEMS). This effort offers the promise of: 1. Increasing the performance and manufacturability of both sensors and actuators by exploiting new batch fabrication processes developed for the IC and microelectronics industry. Examples include micro stereo lithographic and micro molding techniques. 2. Developing novel classes of materials and mechanical structures not possible previously, such as diamond like carbon, silicon carbide and carbon nanotubes, micro-turbines and micro-engines. 3. Development of technologies for the system level and wafer level integration of micro components at the nanometer precision, such as self-assembly techniques and robotic manipulation. 4. Development of control and communication systems for MEMS devices, such as optical and RF wireless, and power delivery systems.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Journey Toward Process Convergence in TSV Technology

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001282-001321
Author(s):  
Sesh Ramaswami ◽  
John Dukovic
Keyword(s):  
Process Integration ◽  
Semiconductor Industry ◽  
Rapid Development ◽  
Chemical Mechanical Planarization ◽  
Cost Effective ◽  
Superior Performance ◽  
Wafer Level ◽  
Unit Process ◽  
Integration Schemes ◽  
Process Convergence

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP). Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products. This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.

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