Highly Integrated Power Managemant Integrated Circuits in Advanced Cmos Process Technologies

2008 ◽  
pp. 303-316
Author(s):  
Mario Manninger
Keyword(s):  
Integrated Circuits ◽  
Cmos Process

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

FEATURES OF THE TECHNOLOGICAL PROCESS OF MANUFACTURING SPACE-BASED MICROCHIPS USING CMOS KNS TECHNOLOGY

2020 ◽  
Vol 13 (3) ◽  
pp. 53-58
Author(s):  
Vladimir Zolnikov ◽  
Svetlana Evdokimova ◽  
Irina ZHuravlyeva ◽  
Elena Maklakova ◽  
Anna Ilunina
Keyword(s):  
Integrated Circuits ◽  
Technological Process ◽  
Cmos Integrated Circuits ◽  
Cmos Process

The article deals with the technological process of manufacturing CMOS integrated circuits on KNS (silicon on sapphire) structures for space purposes. The technology is based on an n-type CMOS process with one level of polysilicon and two levels of metal. The components of the technological process are analyzed. The sequence of the technological process and its features are given. An example of a description of one of the elements is considered.

A High-Performance Interface ASIC for Quartz Rate Sensor

2011 ◽  
Vol 483 ◽  
pp. 471-474
Author(s):  
Wei Ping Chen ◽  
Qing Yi Wang ◽  
Liang Yin ◽  
Zhi Ping Zhou
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Performance ◽  
Low Noise ◽  
Stable Operation ◽  
Cmos Process ◽  
Test Results ◽  
Bias Stability ◽  
Output Noise ◽  
Rate Sensor

In this work, an ASIC interface for quartz rate sensor (QRS) is introduced. Based on 0.6μm 18V N-well CMOS process, it is the first to be realized in the domestic. This chip has a minimized size of 5×4.4mm2. Compared with traditional interface constructed by separate devices, such interface implemented with integrated circuits is advantageous in size and power consumption. This satisfies the requirements of miniature and low power consumption in space industry and military domain. The test results show that this interface features low noise, high linearity, and stable operation. Integrated with the sensor, the entire system presents high performance in short term bias stability, nonlinearity, output noise, bias variation over temperature, and power consumption.

Design of a High Performance CMOS Bandgap Voltage Reference

2014 ◽  
Vol 981 ◽  
pp. 90-93
Author(s):  
Yang Guang ◽  
Bin Yu ◽  
Huang Hai
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Circuit Simulation ◽  
Absolute Temperature ◽  
Reference Voltage ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Changes ◽  
Bandgap Voltage Reference ◽  
Protection Circuit

Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.

An Improved CAL Register File with Dual-Threshold Technique for Leakage Reduction

2010 ◽  
Vol 159 ◽  
pp. 186-191 ◽  
Author(s):  
Jian Ping Hu ◽  
Jia Guo Zhu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Total Power ◽  
Cmos Process ◽  
Register File ◽  
Mos Transistors ◽  
Leakage Currents ◽  
Micro Power ◽  
Scaling Down ◽  
Threshold Technique

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. The leakage dissipation caused by leakage currents is becoming an increasingly important fraction of the total power dissipation in nanometer integrated circuits. To decrease leakage power dissipations is becoming more and more important in micro-power nanometer circuits. An improved CAL register file using DTCMOS (Dual-Threshold Technique) for reducing leakage dissipations in active mode is addressed in this paper. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE at 45nm CMOS process. Simulation results show that the register file with dual-threshold can reduce about 15.6% power dissipations.

scholarly journals Resonant Rectifier ICs for Piezoelectric Energy Harvesting Using Low-voltage Drop Diode Equivalents

2017 ◽  
Author(s):  
Amad Ud Din ◽  
Seneke Chamith Chandrathna ◽  
Jong-Wook Lee
Keyword(s):  
Energy Harvesting ◽  
Integrated Circuits ◽  
Low Voltage ◽  
Voltage Drop ◽  
Power Conversion ◽  
Cmos Process ◽  
Power Extraction ◽  
Piezoelectric Energy ◽  
Bridge Rectifier ◽  
External Power

Herein, we present the design technique of a resonant rectifier for piezoelectric (PE) energy harvesting. We propose two diode equivalents to reduce the voltage drop in the rectifier operation, a minuscule-drop-diode equivalent (MDDE) and a low-drop-diode equivalent (LDDE). The diode equivalents are embedded in resonant rectifier integrated circuits (ICs), which use symmetric bias-flip to reduce the power wasted for charging and discharging the internal capacitance of a PE transducer. The self-startup function is supported by synchronously generating control pulses for the bias-flip from the PE transducer. Two resonant rectifier ICs, using both MDDE and LDDE, are fabricated in a 0.18 μm CMOS process and their performances are characterized under external and self-power conditions. Under the external-power condition, the rectifier using LDDE delivers an output power POUT of 564 μW and a rectifier output voltage VRECT of 3.36 V with a power conversion efficiency (PCE) of 90.1%. Under self-power conditions, the rectifier using MDDE delivers a POUT of 288 μW and a VRECT of 2.4 V with a corresponding PCE of 74.6%. The result shows that the power extraction capability of the proposed rectifier is 5.9 and 3.0 times higher than that of a conventional full-bridge rectifier.

500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000076-000083 ◽  
Author(s):  
Paul Shepherd ◽  
Ashfaqur Rahman ◽  
Shamim Ahmed ◽  
A Matt Francis ◽  
Jim Holmes ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Extreme Environments ◽  
Phase Locked Loops ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Fully Integrated ◽  
Improved Performance

Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

Digital and Analogue Integrated Circuits in Silicon Carbide for High Temperature Operation

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000373-000377 ◽  
Author(s):  
E.P Ramsay ◽  
D.T. Clark ◽  
J.D. Cormack ◽  
A.E. Murphy ◽  
D.A Smith ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Nand Gate ◽  
Cmos Process ◽  
Flip Flop ◽  
Aero Engines ◽  
Simple Logic ◽  
High Temperature Operation

A need for high temperature integrated circuits is emerging in a number of application areas. As Silicon Carbide power discrete devices become more widely available, there is a growing need for control ICs capable of operating at the same temperatures and mounted on the same modules. Also, the use of high temperature sensors, in, for example, aero engines and in deep hydrocarbon and geothermal drilling applications results in a demand for high temperature sensor interface ICs. This paper presents new results on a range of simple logic and analogue circuits fabricated on a developing Silicon Carbide CMOS process which is intended for mixed signal integrated circuit applications such as those above. A small family of logic circuits, pin compatible with the 74xx series TTL logic parts, has been designed, fabricated and tested and includes, for example, a Quad Nand gate and a Dual D-type flip-flop. These have been found to be functional from room temperature up to 400°C. Analogue blocks have been investigated with a view to using switched capacitor or autozero techniques to compensate for temperature and time induced drifts, allowing very high temperature operation.

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