500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000076-000083 ◽  
Author(s):  
Paul Shepherd ◽  
Ashfaqur Rahman ◽  
Shamim Ahmed ◽  
A Matt Francis ◽  
Jim Holmes ◽  
...  

Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000373-000377 ◽  
Author(s):  
E.P Ramsay ◽  
D.T. Clark ◽  
J.D. Cormack ◽  
A.E. Murphy ◽  
D.A Smith ◽  
...  

A need for high temperature integrated circuits is emerging in a number of application areas. As Silicon Carbide power discrete devices become more widely available, there is a growing need for control ICs capable of operating at the same temperatures and mounted on the same modules. Also, the use of high temperature sensors, in, for example, aero engines and in deep hydrocarbon and geothermal drilling applications results in a demand for high temperature sensor interface ICs. This paper presents new results on a range of simple logic and analogue circuits fabricated on a developing Silicon Carbide CMOS process which is intended for mixed signal integrated circuit applications such as those above. A small family of logic circuits, pin compatible with the 74xx series TTL logic parts, has been designed, fabricated and tested and includes, for example, a Quad Nand gate and a Dual D-type flip-flop. These have been found to be functional from room temperature up to 400°C. Analogue blocks have been investigated with a view to using switched capacitor or autozero techniques to compensate for temperature and time induced drifts, allowing very high temperature operation.


Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.


MRS Bulletin ◽  
2015 ◽  
Vol 40 (5) ◽  
pp. 431-438 ◽  
Author(s):  
Carl-Mikael Zetterling

Abstract


2011 ◽  
Vol 679-680 ◽  
pp. 726-729 ◽  
Author(s):  
David T. Clark ◽  
Ewan P. Ramsay ◽  
A.E. Murphy ◽  
Dave A. Smith ◽  
Robin. F. Thompson ◽  
...  

The wide band-gap of Silicon Carbide (SiC) makes it a material suitable for high temperature integrated circuits [1], potentially operating up to and beyond 450°C. This paper describes the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.


2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.


MRS Bulletin ◽  
1992 ◽  
Vol 17 (8) ◽  
pp. 34-38 ◽  
Author(s):  
Ronald H. Ono

The realization of a revolutionary generation of electronics based on high-temperature superconductors (HTS) crucially depends on the ability to make high-quality thin film microstructures. These will incorporate materials such as YBa2Cu3O7-δ (YBCO), TlBaCaCuO, or BiSrCaCuO in a fashion similar to the circuits and devices made of their low Tc counterparts Nb or NbN. Without exception, the most valuable structures will be composed of multiple layers of superconducting films and dielectrics, in some cases combined with normal metals, low-temperature superconductors, or a variety of semiconductors. Generically, these can be combined in two ways: in a hybrid design where specialized packages and bonding are used to attach dissimilar materials, or in a monolithic thin film structure such as the one seen in Figure 1.The division between hybrid and monolithic multilayers results from the historical development of electronic circuits. Hybrid designs typically require linewidths and alignment accuracy somewhat less demanding than those used in fully integrated circuits. The advantage of hybrid construction is the separation of incompatible processing steps onto different substrates or die. The monolithic integrated circuit, whether microelectronic, millimeter wave, or radio frequency, can be made in large batches with concomitant economy of scale and can be fabricated with fewer parasitic constraints. Superconducting integrated circuits have followed the semiconductor pattern of being developed in a hybrid fashion, then transferred to a fully integrated process.


2012 ◽  
Vol 717-720 ◽  
pp. 1261-1264 ◽  
Author(s):  
Amita Patil ◽  
Naresh Rao ◽  
Vinayak Tilak

This paper pertains to development of high temperature capable digital integrated circuits in n-channel, enhancement-mode Silicon Carbide (SiC) MOS technology. Among the circuits developed in this work are data latch, flip flops, 4-bit shift register and ripple counter. All circuits are functional from room temperature up to 300C without any notable degradation in performance at elevated temperature. The 4-bit counter demonstrated stable behavior for over 500 hours of continuous operation at 300C.


2013 ◽  
Vol 58 (4) ◽  
pp. 375-388 ◽  
Author(s):  
M. Alexandru ◽  
V. Banu ◽  
J. Montserrat ◽  
P. Godignon ◽  
J. Millan

2017 ◽  
Vol 2017 (1) ◽  
pp. 000526-000530
Author(s):  
M. Barlow ◽  
A. M. Francis ◽  
J. Holmes

Abstract Silicon carbide integrated circuits have demonstrated the ability to function at temperatures as high as 600 °C for extended periods of time. Many environments where high temperature in-situ electronics are desired also have large pressures as well. While some validation has been done for high pressure environments, limited information on the parametric impact of pressure on SiC integrated circuits is available. This paper takes two leading-edge SiC integrated circuit processes using two different classes of devices (JFET and CMOS), and measures the performance through temperature and pressure variation. Circuit functionality was verified at high temperature (475 °C) as well as high pressure (1700 psig).


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