scholarly journals A modular approach for testable conservative reversible multiplexer circuit for nano-electronic confine application

2019 ◽  
Vol 9 (4) ◽  
pp. 299-309 ◽  
Author(s):  
Nirupma Pathak ◽  
Santosh Kumar ◽  
Neeraj Kumar Misra ◽  
Bandan Kumar Bhoi
Keyword(s):  
Control Unit ◽  
System Level ◽  
Quantum Cost ◽  
Optimal Parameters ◽  
Gate Count ◽  
Reversible Circuit ◽  
Art Works ◽  
Computing Framework ◽  
Quantum Technology ◽  
State Of Art

Abstract Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm, which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count, quantum cost and unit delay are optimal.

scholarly journals Synthesis of reversible circuits for large reversible functions

2010 ◽  
Vol 23 (3) ◽  
pp. 273-286 ◽  
Author(s):  
Nouraddin Alhagi ◽  
Maher Hawash ◽  
Marek Perkowski
Keyword(s):  
Data Structure ◽  
Real Time ◽  
Large Scale ◽  
Optimal Solution ◽  
Truth Table ◽  
Synthesis Process ◽  
Quantum Cost ◽  
Reversible Circuits ◽  
Gate Count ◽  
Reversible Circuit

This paper presents a new algorithm MP (multiple pass) to synthesize large reversible binary circuits without ancilla bits. The well-known MMD algorithm for synthesis of reversible circuits requires to store a truth table (or a Reed-Muller - RM transform) as a 2n vector to represent a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with any existing algorithm. In addition, our unique multi-pass approach where the circuit is synthesized with various, yet specific, minterm orders yields quasi-optimal solution. The algorithm returns a description of the quasi-optimal circuit with respect to gate count or to its 'quantum cost'. Although the synthesis process in MP is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less.

scholarly journals A shared-cube approach to ESOP-based synthesis of reversible logic

2011 ◽  
Vol 24 (3) ◽  
pp. 385-402 ◽  
Author(s):  
Noor Nayeem ◽  
Jacqueline Rice
Keyword(s):  
Power Loss ◽  
Heat Dissipation ◽  
Logic Synthesis ◽  
Reversible Logic ◽  
Experimental Results ◽  
Quantum Cost ◽  
Toffoli Gate ◽  
Gate Count ◽  
Computing Industry ◽  
Synthesis Approach

Reversible logic is being suggested as a possibility for overcoming potential power loss and heat dissipation problems that the computing industry may soon be at a loss to overcome. However, for reversible logic to be a solution we must have techniques for synthesizing function descriptions to reversible circuits. This paper presents an improved ESOP-based reversible logic synthesis approach which leverages situations where cubes are shared by multiple outputs and ensures that the implementation of each cube requires just one Toffoli gate. It has the potential to minimize both gate count and quantum cost, and in fact our experimental results show that this technique can reduce the quantum cost up to 75% compared to results from the existing work.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

An Efficient Design for Testability Approach of Reversible Logic Circuits

2020 ◽  
pp. 2150094
Author(s):  
Joyati Mondal ◽  
Arighna Deb ◽  
Debesh K. Das
Keyword(s):  
Fault Detection ◽  
Low Power Design ◽  
Design For Testability ◽  
Control Input ◽  
Quantum Cost ◽  
Efficient Design ◽  
Additional Line ◽  
Reversible Circuits ◽  
Reversible Circuit ◽  
Additional Input

Reversible circuits have been extensively investigated because of their applications in areas of quantum computing or low-power design. A reversible circuit is composed of only reversible gates and allow computations from primary inputs to primary outputs and vice-versa. In the last decades, synthesis of reversible circuits received significant interest. Additionally, testing of these kinds of circuits has been studied which included different fault models and test approaches dedicated for reversible circuits only. The analysis of testability issues in a reversible circuit commonly involves the detection of the missing gate faults that may occur during the physical realizations of the reversible gates. In this paper, we propose a design for testability (DFT) technique for reversible circuits in which the gates of a circuit are clustered into different sets and the gates from each cluster are then connected to an additional input line where, the additional line acts as an extra control input to the corresponding gate. Such arrangement makes it possible to achieve [Formula: see text] fault detection in any reversible circuit with a small increase in quantum cost. Experimental evaluations confirm that the proposed DFT technique incurs less quantum cost overhead with [Formula: see text] fault detection compared to existing DFT techniques for reversible circuits.

Research on an Approximate Model Based Virtual Calibration Method With DoE and Optimization Algorithm for Transmission Control Unit

2013 ◽  
Author(s):  
Guangqiang Wu ◽  
Lu Sun ◽  
Sheng Zhu ◽  
Kuankuan Zhang
Keyword(s):  
Subjective Experience ◽  
Automatic Transmission ◽  
Control Unit ◽  
Calibration Method ◽  
Approximate Model ◽  
Optimal Parameters ◽  
Latin Hypercube Design ◽  
Transmission Control ◽  
The Neural Network ◽  
Optimal Latin Hypercube Design

In order to solve the problems arising from the manual calibration method in the developing process of vehicle automatic transmission control unit (TCU), known as time-consuming, heavy workload, high cost and over-dependence on subjective experience, this article researches on a virtual calibration method based on an approximate model to obtain optimal parameters for TCU. The neural network approximate model is established from the test data chosen with the method of DoE (Design of Experiment). The virtual calibration method is then conducted through Optimal Latin Hypercube Design (OLHD) and multi-island genetic algorithm (MIGA) to search the optimal parameters. By comparing the new calibration method with original manual one on the condition of gear 1 up to gear 2, the result shows that the new method can increase the efficiency significantly.

Efficient designs of reversible BCD to EX-3 Converter with low quantum cost in nanoscale

2020 ◽  
Vol 18 (05) ◽  
pp. 2050020 ◽  
Author(s):  
Mojtaba Noorallahzadeh ◽  
Mohammad Mosleh
Keyword(s):  
Quantum Computing ◽  
Optical Computing ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Computing Systems ◽  
Gate Count ◽  
Reversible Gate ◽  
Significant Research ◽  
Research Domain ◽  
Better Than

As an interesting and significant research domain, reversible logic is massively utilized in technologies, including optical computing, cryptography, quantum computing, nanotechnology, and so on. The realization of quantum computing is not possible without the implementation of reversible logic, and reversible designs are presented mainly to minimize the thermal loss because of the data input bits lost in the irreversible circuit. Digital converters, as the most important logic circuits, are used to connect computing systems with different binary codes. This paper first proposes a new reversible gate called Reversible Noorallahzadeh[Formula: see text]Mosleh Gate (RNMG). Then, using the proposed RNMG gate as well as existing NMG1, NMG6, and PG gates, three different designs of reversible Binary-Coded Decimal (BCD) to EX-3 code converter are proposed. Our results indicate that the proposed BCD to EX-3 code converters are superior to previous designs in terms of quantum cost. Moreover, the proposed converters are comparable or better than previous designs in terms of gate count, constant inputs, and garbage outputs.

Virtual Verification and Validation of Automotive System

2019 ◽  
Vol 28 (04) ◽  
pp. 1950071
Author(s):  
Mona Safar ◽  
Magdy A. El-Moursy ◽  
Mohamed Abdelsalam ◽  
Ayman Bakr ◽  
Keroles Khalil ◽  
...  
Keyword(s):  
Fault Injection ◽  
Electronic Control Unit ◽  
Control Unit ◽  
Verification And Validation ◽  
System Level ◽  
Development Cycle ◽  
Virtual Platform ◽  
On Chip ◽  
Automotive System

An integrated framework for Virtual Verification and Validation (VVV) for a complete automotive system is proposed. The framework can simulate/emulate the system on three levels: System on Chip (SoC), Electronic control unit (ECU) and system level. The framework emulates the real system including hardware (HW) and software (SW). It enhances the automotive V-cycle and allows co-development of the automotive system SW and HW. The procedure for debugging AUTOSAR application on the virtual platform (VP) is shown. SW and HW profiling is feasible with the presented methodology. Verification and validation of automotive embedded SW is also presented. The proposed methodology is efficient as the system complexity increases which shortens the development cycle of automotive system. It also provides fault injection capability. With HW emulation, co-debugging mechanism is demonstrated. A case study covering the framework capability is presented. The case study demonstrates the proposed framework and methodology to design, simulate, trace, profile and debug AUTOSAR SW using VPs.

Displacement Amplifying Compliant Mechanisms for Two-Axis High-Resolution Monolithic Inertial Sensors

2008 ◽  
Author(s):  
M. Dinesh ◽  
G. K. Ananthasuresh
Keyword(s):  
High Resolution ◽  
Building Block ◽  
Proof Mass ◽  
Compliant Mechanisms ◽  
Inertial Sensors ◽  
System Level ◽  
Optimal Parameters ◽  
Mass Sensitivity ◽  
System Level Simulation ◽  
Single Piece

Novel designs for two-axis, high-resolution, monolithic inertial sensors are presented in this paper. Monolithic, i.e., joint-less single-piece compliant designs are already common in micromachined inertial sensors such as accelerometers and gyroscopes. Here, compliant mechanisms are used not only to achieve de-coupling between motions along two orthogonal axes but also to amplify the displacements of the proof-mass. Sensitivity and resolution capabilities are enhanced because the amplified motion is used for sensing the measurand. A particular symmetric arrangement of displacement-amplifying compliant mechanisms (DaCMs) leads to de-coupled and amplified motion. An existing DaCM and a new topology-optimized DaCM are presented as a building block in the new arrangement. A spring-mass-lever model is presented as a lumped abstraction of the new arrangement. This model is useful for arriving at the optimal parameters of the DaCM and for performing system-level simulation. The new designs improved the performance by a factor of two or more.

scholarly journals First comparison of the electrical properties of two grid emulators for UVRT test against field measurement

2021 ◽  
Author(s):  
Anica Frehn ◽  
Soroush Azarian ◽  
Gesa Quistorf ◽  
Stephan Adloff ◽  
Fritz Santjer ◽  
...  
Keyword(s):  
Wind Turbine ◽  
Field Measurement ◽  
Test Bench ◽  
Voltage Divider ◽  
System Level ◽  
Hardware In The Loop ◽  
Extra High Voltage ◽  
First Time ◽  
State Of Art ◽  
Technical Rules

AbstractThe technical rules for connecting turbines to the medium, high or extra-high voltage grid in Germany require the certification of the UVRT characteristics of wind turbines. The state-of-art voltage divider-based test equipment, also named UVRT-Container, is well equipped for executing UVRT tests in field. To conduct the UVRT in field the full wind turbine should be already installed. A second option to perform UVRT tests are system level test benches. They enable the testing of the nacelle. The components that are not actually present, such as the turbine tower or the blades, are emulated via a mechanical hardware in the loop (HiL) system. In this work, for the first time, the performance of two different grid simulators installed at the DyNaLab at Fraunhofer IWES and at the CWD at RWTH Aachen University is compared with a field measurement of the same type of wind turbine. Thus, not only a system test bench measurement is compared to a field measurement. Rather, two system test benches with individual technical approaches are additionally compared with each other. The focus of this work is to investigate the characteristics of the grid simulators within the steady-state range of the UVRT tests to replicate identical fault shapes on the test benches and in the field.

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