Light Emission to Time Resolved Emission For IC Debug and Failure Analysis

2005 ◽  
Vol 45 (9-11) ◽  
pp. 1476-1481 ◽  
Author(s):  
M. Remmach ◽  
A. Pigozzi ◽  
R. Desplats ◽  
P. Perdu ◽  
D. Lewis ◽  
...  
Author(s):  
J.A. Kash ◽  
J.C. Tsang ◽  
D.R. Knebel ◽  
D.P. Vallett

Abstract A noninvasive backside probe of integrated circuits has been developed. This new probe can diagnose at-speed failures, stuck faults, and other defects. Because it is a highly parallel imaging technique, faults may be isolated which are difficult to locate by other methods. This optical technique has been named “PICA”, for picosecond imaging circuit analysis. PICA relies on the fact that an FET in a CMOS circuit emits a picosecond pulse of light each time the logic gate changes state. The source of this emission is explained. The PICA technique, which combines optical imaging of the emission with picosecond time-resolution, is described. Because of the imaging, time-resolved emission data is acquired for many transistors in parallel. The use of the emission for failure analysis and AC characterization of integrated circuits is demonstrated. Because the emission can be detected from either the front or back side of the chip, it can be used for both front and back side analysis.


Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.


Author(s):  
Thierry Parrassin ◽  
Sylvain Dudit ◽  
Michel Vallet ◽  
Antoine Reverdy ◽  
Hervé Deslandes

Abstract By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.


Author(s):  
Yoav Weizman ◽  
Ezra Baruch

Abstract In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap. This inherent wavelength limitation, together with the shrinking dimensions of modern CMOS devices, limit the capabilities of these tools. It is known that the optical resolution limits of the LVP and TRLEM techniques are bounded by the diffraction limit which is ~1um for both tools using standard optics. This limitation was reduced with the addition of immersion lens optics. Nevertheless, even with this improvement, shrinking transistor geometry is leading to increased acquisition time, and the overlapping effect between adjacent nodes remains a critical issue. The resolution limit is an order of magnitude above the device feature densities in the < 90nm era. The scaling down of transistor geometry is leading to the inevitable consequence where more than 50% of the transistors in 90nm process have widths smaller than 0.4um. The acquisition time of such nodes becomes unreasonably long. In order to examine nodes in a dense logic cuicuit, cross talk and convolution effects between neighboring signals also need to be considered. In this paper we will demonstrate the impact that these effects may have on modern design. In order to maintain the debug capability, with the currently available analytical tools for future technologies, conceptual modification of the FA process is required. This process should start on the IC design board where the VLSI designer should be familiar with FA constraints, and thus apply features that will enable enhanced FA capabilities to the circuit in hand during the electrical design or during the physical design stages. The necessity for reliable failure analysis in real-time should dictate that the designer of advanced VLSI blocks incorporates failure analysis constraints among other design rules. The purpose of this research is to supply the scientific basis for the optimal incorporation of design rules for optical probing in the < 90nm gate era. Circuit designers are usually familiar with the nodes in the design which are critical for debug, and the type of measurement (logic or DC level) they require. The designer should enable the measurement of these signals by applying certain circuit and physical constraints. The implementation of these constraints may be done at the cell level, the block level or during the integration. We will discuss the solutions, which should be considered in order to mitigate tool limitations, and also to enable their use for next generation processes.


Author(s):  
Jonathan Shaw ◽  
Christopher McMahon ◽  
Yin Shyang Ng ◽  
Félix Beaudoi

Abstract This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.


Author(s):  
Peter Ouimet ◽  
Jason Goertz ◽  
Olivier Rinaudo ◽  
Lousinda Long ◽  
Simon Yeung

Abstract This paper describes case histories of 0.13 um bulk CMOS technology analyses using Time Resolved Light Emission (TRLEM). Using this technique, scan chain, timing, and logic failures are shown to be quickly and decisively identified thereby meeting the need for rapid feedback on 1st silicon failures and process excursions.


Author(s):  
Thomas Ziemann ◽  
Alexander Tsibizov ◽  
Bhagyalakshmi Kakarla ◽  
Lorenz Bort ◽  
Ulrike Grossner

2010 ◽  
Vol 428-429 ◽  
pp. 475-478 ◽  
Author(s):  
Bao Gai Zhai ◽  
Yuan Ming Huang

The optical properties and electronic structures of an organic semiconductor sexithiophene have been investigated with ultraviolet-visible spectroscopy, cw photospectroscopy and time-resolved photospectroscopy, respectively. Sexithiophene in dilute tetrahydrofuran solutions can absorb photons at 400 nm while it can give off strong green photoluminescence at 550 nm under the excitation of 325 nm ultraviolet light. With the assistance of calculated electronic structures and pump-and-probe characterization, our results indicate that both the optical absorption and the light emission of the sexithiophene are controlled by the p-conjugation of the oligothiophene.


1999 ◽  
Vol 32 (7) ◽  
pp. 785-789
Author(s):  
N Georgescu ◽  
G Sandolache ◽  
V Zoita

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