Scan chain failure analysis using laser voltage imaging

2010 ◽  
Vol 50 (9-11) ◽  
pp. 1422-1426 ◽  
Author(s):  
Joy Y. Liao ◽  
Steven Kasapi ◽  
Bruce Cory ◽  
Howard Lee Marks ◽  
Yin S. Ng
Keyword(s):  
Failure Analysis ◽  
Voltage Imaging ◽  
Scan Chain

Scan-Shift Debug Using LVI Phase Mapping

2013 ◽  
Author(s):  
Yin (Roy) S. Ng ◽  
Howard Marks ◽  
Christopher Nemirov ◽  
Chun-Cheng Tsao ◽  
Jim Vickers
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Continuous Wave Laser ◽  
Success Rates ◽  
Established Method ◽  
Electrical Failure ◽  
Voltage Imaging ◽  
Integrity Tests ◽  
Scan Chain ◽  
Domain Information

Abstract Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented.

Failure Analysis Enhancement by Incorporating a Compact Scan Diagnosis System

2014 ◽  
Author(s):  
Rommel Estores ◽  
Pascal Vercruysse ◽  
Karl Villareal ◽  
Eric Barbian ◽  
Ralph Sanchez ◽  
...  
Keyword(s):  
Data Analysis ◽  
Failure Analysis ◽  
Real Analysis ◽  
Failure Data ◽  
Analysis Methodology ◽  
Efficiency And Effectiveness ◽  
Scan Chain ◽  
On Chip ◽  
Analysis Environment ◽  
Selection Of

Abstract The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.

Thermal Frequency Imaging: A New Application of Laser Voltage Imaging Applied on 40nm Technology

2011 ◽  
Author(s):  
Guillaume Celi ◽  
Sylvain Dudit ◽  
Thierry Parrassin ◽  
Philippe Perdu ◽  
Antoine Reverdy ◽  
...  
Keyword(s):  
Charge Carrier ◽  
Laser Beam ◽  
Integrated Circuit ◽  
Carrier Density ◽  
Deep Submicron ◽  
Charge Carrier Density ◽  
Voltage Imaging ◽  
A New Technique ◽  
Scan Chain

Abstract For Very Deep submicron Technologies, techniques based on the analysis of reflected laser beam properties are widely used. The Laser Voltage Imaging (LVI) technique, introduced in 2009, allows mapping frequencies through the backside of integrated circuit. In this paper, we propose a new technique based on the LVI technique to debug a scan chain related issue. We describe the method to use LVI, usually dedicated to frequency mapping of digital active parts, in a way that enables localization of resistive leakage. Origin of this signal is investigated on a 40nm case study. This signal can be properly understood when two different effects, charge carrier density variations (LVI) and thermo reflectance effect (Thermal Frequency Imaging, TFI), are taken into account.

Laser Voltage Imaging: A New Perspective of Laser Voltage Probing

2010 ◽  
Author(s):  
Yin S. Ng ◽  
Ted Lundquist ◽  
Dmitry Skvortsov ◽  
Joy Liao ◽  
Steven Kasapi ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Functional Failure ◽  
Voltage Imaging ◽  
Laser Probing ◽  
New Perspective

Abstract Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.

Yield and Failure Analysis of FinFET Source to Drain Leakage in 12nm Technology

2020 ◽  
Author(s):  
Felix Beaudoin ◽  
Satish Kodali ◽  
Rohan Deshpande ◽  
Wayne Zhao ◽  
Edmund Banghart ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Fault Localization ◽  
Detailed Characterization ◽  
Laser Stimulation ◽  
Emission Microscopy ◽  
Scan Chain ◽  
Multiple Samples ◽  
Tem Lamella ◽  
Diffusion Activation

Abstract Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

A SAT-Based Pattern Generation Method for Diagnosis Multiple Scan Chain Faults

2011 ◽  
Vol 301-303 ◽  
pp. 989-994
Author(s):  
Fei Wang ◽  
Da Wang ◽  
Hai Gang Yang
Keyword(s):  
Failure Analysis ◽  
Design For Testability ◽  
Pattern Generation ◽  
Diagnostic Process ◽  
High Quality ◽  
Analysis Process ◽  
Short Period ◽  
Multiple Scan ◽  
Scan Chain ◽  
Scan Chain Design

Scan chain design is a widely used design-for-testability (DFT) technique to improve test and diagnosis quality. However, failures on scan chain itself account for up to 30% of chip failures. To diagnose root causes of scan chain failures in a short period is vital to failure analysis process and yield improvements. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a SAT-based technique is proposed to generate patterns to diagnose scan chain faults. The proposed work can efficiently generate high quality diagnostic patterns to achieve high diagnosis resolution. Moreover, the computation overhead of proving equivalent faults is reduced. Experimental results on ISCAS’89 benchmark circuits show that the proposed method can reduce the number of diagnostic patterns while achieving high diagnosis resolution.

Effective scan chain failure analysis method

2017 ◽  
Vol 76-77 ◽  
pp. 201-213 ◽  
Author(s):  
Etienne Auvray ◽  
Paul Armagnat ◽  
Luc Saury ◽  
Maheshwaran Jothi ◽  
Michael Brügel
Keyword(s):  
Failure Analysis ◽  
Analysis Method ◽  
Scan Chain

Application of Advanced Back-Side Optical Techniques in ASICs

2013 ◽  
Vol 21 (3) ◽  
pp. 30-35
Author(s):  
Douglas Martin ◽  
Samuel Beilin ◽  
Brett Hamilton ◽  
Darin York ◽  
Philip Baker ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Photon Emission ◽  
Back Side ◽  
Voltage Imaging ◽  
Root Cause ◽  
Silicon Transistors ◽  
Cause Of Failure ◽  
Metal Interconnects ◽  
Application Specific

Failure analysis is important in determining root cause for appropriate corrective action. In order to perform failure analysis of microelectronic application-specific integrated circuits (ASICs) delidding the device is often required. However, determining root cause from the front side is not always possible due to shadowing effects caused by the ASIC metal interconnects. Therefore, back-side polishing is used to reveal an unobstructed view of the ASIC silicon transistors. This paper details how back-side polishing in conjunction with laser-scanned imaging (LSI), laser voltage imaging (LVI), laser voltage probing (LVP), photon emission microscopy (PEM), and laser-assisted device alterations (LADA) were used to uncover the root cause of failure of two ASICs.

Scan Chain Debug Using Dynamic Lock-In Thermography

2011 ◽  
Author(s):  
L. Forli ◽  
B. Picart ◽  
A. Reverdy ◽  
R. Schlangen
Keyword(s):  
Failure Analysis ◽  
Efficient Solution ◽  
Use Cases ◽  
Thermal System ◽  
Complementary Technique ◽  
Scan Chain ◽  
Lock In

Abstract In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.

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