scholarly journals Experimental validation of new self-voltage balanced 9L-ANPC inverter for photovoltaic applications

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
M. Jagabar Sathik ◽  
Dhafer J. Almakhles ◽  
N. Sandeep ◽  
Marif Daula Siddique

AbstractMultilevel inverters play an important role in extracting the power from renewable energy resources and delivering the output voltage with high quality to the load. This paper proposes a new single-stage switched capacitor nine-level inverter, which comprises an improved T-type inverter, auxiliary switch, and switched cell unit. The proposed topology effectively reduces the DC-link capacitor voltage and exhibits superior performance over recently switched-capacitor inverter topologies in terms of the number of power components and blocking voltage of the switches. A level-shifted multilevel pulse width modulation scheme with a modified triangular carrier wave is implemented to produce a high-quality stepped output voltage waveform with low switching frequency. The proposed nine-level inverter’s effectiveness, driven by the recommended modulation technique, is experimentally verified under varying load conditions. The power loss and efficiency for the proposed nine-level inverter are thoroughly discussed with different loads.

Author(s):  
Tamiru Debela ◽  
Jiwanjot Singh

Abstract Multilevel inverters (MLIs) have formed a new wave of interest in research and industry. Switched capacitor-based multilevel inverters are used to avoid the need for multiple separated DC sources compared to cascaded MLIs. However, the inclusion of several capacitors creates problems such as high inrush current, voltage imbalance. To avoid these drawbacks, this paper proposes an isolation-based scheme by using a flyback converter in the switched capacitor multilevel inverter. Further, the overall topology provides step-up AC voltage across the load from a single DC source with fewer power switches. To generate a step-up five-level voltage across the load, switched capacitor-based multilevel inverter needs six power switches and only one capacitor. To get the appropriate switching operation to generate the NL-levels, phase disposition pulse width modulation (PD-PWM) has been developed. The extended nine-level S 2 -MLI is also discussed in this paper under different conditions as change in input source voltage and dynamic load change. Moreover, to prove the superior performance of switched-capacitor single DC source multilevel inverter (S2-MLI), comparative analysis with existing single DC source MLI has been performed. The effectiveness and feasibility of the proposed topology are tested with varieties of loads by simulation using Matlab/Simulink. To validate the simulation results, hardware implementation has been done of five-level S2-MLI considering resistive and motor load by using DSpace 1103 controller.


Multilevel inverters are widely used for high power and high voltage applications. The performance of multilevel inverters are superior to conventional two level inverters in terms of reduced total harmonic distortion, higher dc link voltages, lower electromagnetic interference and increased quality in the output voltage waveform. This paper presents a single phase hybrid eleven level multilevel inverter topology with reduced switch count to compensate the above mentioned disadvantages. This paper also presents various high switching frequency based multi carrier pulse width modulation strategies such as Phase Disposition PWM Strategy (PDPWM), Phase Opposition and Disposition PWM Strategy (PODPWM), Alternate Phase opposition Disposition PWM (APODPWM), Carrier Overlapping PWM (COPWM), Variable frequency carrier PWM (VFPWM), Third Harmonic Injection PWM (TFIPWM) applied to the proposed eleven level multilevel inverter and is analyzed for RL load. FFT analysis is carried out and total harmonic distortion, fundamental output voltage are calculated. Simulation is carried out in MATLAB/SMULINK.


Energies ◽  
2021 ◽  
Vol 14 (22) ◽  
pp. 7643
Author(s):  
Lingling Cao ◽  
Jiefeng Lin ◽  
Shikai Chen ◽  
Yuanmao Ye

Multilevel inverters have been widely used in various industrial applications such as renewable energy generation and electric vehicles. An improved circuit of symmetrical cascaded switched-capacitor multilevel inverter is proposed so that the reactive power is absorbed by its power supply instead of capacitors. Then, a special hybrid pulse width modulation strategy combing level-shifted pulse width modulation (LS-PWM) and phase-shifted pulse width modulation (PS-PWM) was developed for the inverter. With this modulation algorithm, the power between cascaded units is automatically balanced, and the voltage of the capacitor in each unit is also automatically balanced to the dc input voltage. In addition, the optimized capacitor voltage ripple makes it possible to use a smaller capacitor to produce a better output voltage waveform. Theoretical analysis, simulation and experimental results show that the equivalent switching frequency of the cascaded multilevel inverter is twice the original frequency so that the output voltage harmonics are only distributed near even multiples of the carrier frequency.


2019 ◽  
Vol 16 (2) ◽  
pp. 422-427
Author(s):  
S. Karthikeyan ◽  
K. Lakshmi ◽  
S. Sivaranjani ◽  
J. Karthika ◽  
T. Nandhakumar

Multilevel inverters are mainly used in high power and medium voltage applications to reduce the required voltage rating of the power semiconductor switching devices. Nowadays multilevel inverters are also preferred for various applications regardless of the power ratings because they can essentially realize lower harmonics with lower switching frequency and lower electromagnetic interference (EMI). However, it has some disadvantages such as increased number of components, complex Pulse Width Modulation control method, and voltage balancing problem. In this paper a new topology of cascaded multilevel inverter using reduced number of switches is introduced resulting in higher output voltage levels. There era five series connected H-bridges and the DC voltage is given in the ratio n0: n: n3:2n2:10n. The output voltage having 123 levels is obtained (61 positive voltage levels, 61 negative voltage levels and zero voltage levels). Reduced Total Harmonic Distortion (THD) makes them useful for electric vehicle, FACTS and has given option for various power applications. The proposed topology results in reduction of cost and has simplicity of control system. Therefore, the overall cost and complexity are greatly reduced particularly for higher output voltage levels.


2014 ◽  
Vol 626 ◽  
pp. 141-149 ◽  
Author(s):  
Shibu J.V. Bright ◽  
V. Suba ◽  
S. Ramkumar ◽  
S. Jeevananthan

The pulse width modulation (PWM) strategy employed in the voltage source inverter (VSI) not only control the magnitude of the output voltage but also the quality. Performance evaluations of such strategies are done in terms of fundamental voltage, total harmonic distortion (THD), switching losses etc. (primary indices) and also in terms of acoustic noise, electromagnetic interference (EMI), harmonic spread factor, distribution of harmonic power etc. (secondary indices). Multilevel inverter (MLI) has become unanimous choice in medium and high power applications due to their superior performance compared to three level inverters. The conventional Sub-Harmonic PWM (SHPWM) scheme and its variations offer the output voltage spectrum with high intensity harmonic components around the switching frequency; it will end with cluster harmonic with high acoustic noise. The first objective of this paper is to investigate harmonic spreading effects of existing multilevel inverter (MLI) strategies. Secondly the developing innovative PWM strategies for MLIs based on modified reference and carrier functions, which were proved for superior the primary indices at three-level VSI. Thorough simulation study of Pulse width modulation strategies such as SHPWM, inverted sine carrier PWM, MWM PWM, third harmonic injection PWM, triplen harmonic injection PWM, analog space vector PWM, trapezoidal PWM and discontinuous PWM for a cascaded multilevel inverter, are presented with results of primary and secondary indices. Hence, the PWM strategies of MLI are evaluated for harmonic spreading effect first time and a guide line for a beginner to select the PWM scheme for MLI fed drive systems is stenciled.


Author(s):  
D. Sandhya Rani ◽  
A. Appaprao

Multilevel inverters are increasingly being used in high-power medium voltage applications due to their superior performance compared to two-level inverters. Among various modulation techniques for a multilevel inverter, the space vector pulse width modulation (SVPWM) is widely used. The complexity is due to the difficulty in determining the location of the reference vector, the calculation of ontimes, and the determination and selection of switching states. This paper proposes a general SVPWM algorithm for multilevel inverters based on standard two-level SVPWM. Since the proposed multilevel SVPWM method uses two-level modulation to calculate the on-times, the computation of on-times for an n-level inverter becomes easier. The proposed method uses a simple mapping to achieve the SVPWM for a multilevel inverter. A general n-level implementation is explained, and experimental results are given for two-level and three-level inverters.


Author(s):  
R. Palanisamy ◽  
A. Velu ◽  
K. Selvakumar ◽  
D. Karthikeyan ◽  
D. Selvabharathi ◽  
...  

This paper deals the implementation of 3-level output voltage using dual 2-level inverter with control of sub-region based Space Vector Modulation (SR-SVM). Switching loss and voltage stress are the most important issues in multilevel inverters, for keep away from these problems dual inverter system executed. Using this proposed system, the conventional 3-level inverter voltage vectors and switching vectors can be located. In neutral point clamped multilevel inverter, it carries more load current fluctuations due to the DC link capacitors and it requires large capacitors. Based on the sub-region SVM used to control IGBT switches placed in the dual inverter system. The proposed system improves the output voltage with reduced harmonic content with improved dc voltage utilisation. The simulation and hardware results are verified using matlab/simulink and dsPIC microcontroller.


Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 268 ◽  
Author(s):  
Ali Shojaei ◽  
Bahram Najafi ◽  
Hani Vahedi

In this paper the standalone operation of the modified seven-level Packed U-Cell (MPUC) inverter is presented and analyzed. The MPUC inverter has two DC sources and six switches, which generate seven voltage levels at the output. Compared to cascaded H-bridge and neutral point clamp multilevel inverters, the MPUC inverter generates a higher number of voltage levels using fewer components. The experimental results of the MPUC prototype validate the appropriate operation of the multilevel inverter dealing with various load types including motor, linear, and nonlinear ones. The design considerations, including output AC voltage RMS value, switching frequency, and switch voltage rating, as well as the harmonic analysis of the output voltage waveform, are taken into account to prove the advantages of the introduced multilevel inverter.


Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 263
Author(s):  
Manyuan Ye ◽  
Wei Ren ◽  
Qiwen Wei ◽  
Guizhi Song ◽  
Zhilin Miao

Asymmetric Cascaded H-bridge (ACHB) level inverters can output more voltage waveforms with fewer cascaded units while ensuring the quality of output voltage waveforms, so they have attracted more and more attention. Taking the topology of Type-III asymmetric CHB multilevel inverters as the research object, a Modified Hybrid Frequency Pulse Width Modulation (MHF-PWM) strategy is proposed in this paper. This modulation strategy overcomes the local overshoot of low-voltage unit in the presence of traditional Hybrid Frequency Pulse Width Modulation (HF-PWM), thus completely eliminating the low frequency harmonics in the output voltage waveform of Type-III ACHB nine-level inverters, and the Total Harmonic Distortion (THD) of output line voltage of the modulation strategy is lower than that of PS-PWM strategy in the whole modulation degree, which effectively improves the quality waveform of the output line voltage. At the same time, the strategy can also improve the problems of current backflow and energy feedback caused by the high-voltage unit pouring current to the low-voltage unit, thereby reducing the imbalance of the output power of the high-voltage and low-voltage units. Finally, the Matlab/Simulink simulation model and experimental platform are established to verify the validity and practicality of the modulation strategy.


Energies ◽  
2020 ◽  
Vol 13 (7) ◽  
pp. 1556 ◽  
Author(s):  
Anzar Ahmad ◽  
MU Anas ◽  
Adil Sarwar ◽  
Mohammad Zaid ◽  
Mohd Tariq ◽  
...  

Conventional multilevel inverter topologies like neutral point clamped (NPC), flying capacitor (FC), and cascade H bridge (CHB) are employed in the industry but require a large number of switches and passive and active components for the generation of a higher number of voltage levels. Consequently, the cost and complexity of the inverter increases. In this work, the basic unit of a switched capacitor topology was generalized utilizing a cascaded H-bridge structure for realizing a switched-capacitor multilevel inverter (SCMLI). The proposed generalized MLI can generate a significant number of output voltage levels with a lower number of components. The operation of symmetric and asymmetric configurations was shown with 13 and 31 level output voltage generation, respectively. Self-capacitor voltage balancing and boosting capability are the key features of the proposed SCMLI structure. The nearest level control modulation scheme was employed for controlling and regulating the output voltage. Based on the longest discharging time, the optimum value of capacitance was also calculated. A generalized formula for the generation of higher voltage levels was also derived. The proposed model was simulated in the MATLAB®/Simulink 2016a environment. Simulation results were validated with the hardware implementation.


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