A Novel Design of High Performance and Robust Ultra-Low Power SRAM Cell Based on Memcapacitor

2021 ◽  
Author(s):  
Alireza Abbasi ◽  
Farbod Setoudeh ◽  
Mohammad Bagher Tavakoli ◽  
Ashkan Horri
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Random Access ◽  
Access Memory ◽  
Ultra Low Power ◽  
Cell Parameters ◽  
Consumption Data ◽  
Sram Cell ◽  
Non Volatile Memory ◽  
Novel Design

Abstract The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.

A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

2019 ◽  
Vol 29 (05) ◽  
pp. 2050067
Author(s):  
S. R. Mansore ◽  
R. S. Gamad ◽  
D. K. Mishra
Keyword(s):  
High Performance ◽  
Model Simulation ◽  
Random Access ◽  
Leakage Power ◽  
Access Memory ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Operation Characteristics ◽  
Static Noise

Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.

scholarly journals Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks

2021 ◽  
Vol 11 (3) ◽  
pp. 29
Author(s):  
Tommaso Zanotti ◽  
Francesco Maria Puglisi ◽  
Paolo Pavan
Keyword(s):  
Neural Networks ◽  
High Performance ◽  
Random Access ◽  
Resistive Random Access Memory ◽  
Hardware Accelerators ◽  
Memory Architecture ◽  
Ultra Low Power ◽  
Von Neumann ◽  
Non Volatile Memory ◽  
Volatile Memory

Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >103 times when performing a BNN inference task with respect to a SIMPLY implementation.

scholarly journals Design, Implementation and Analysis of 8T SRAM Cell in Memory Array

2018 ◽  
Vol 7 (3.1) ◽  
pp. 101
Author(s):  
B Kaleeswari ◽  
S Kaja Mohideen
Keyword(s):  
Leakage Current ◽  
Power Analysis ◽  
High Performance ◽  
Random Access ◽  
Vital Role ◽  
Access Memory ◽  
Memory Design ◽  
Design Structure ◽  
Sram Cell ◽  
Scale Down

In modern VLSI designs, static random access memory plays a vital role because of its high performance and low power consumption qualities. As technology is scale down, the importance of the power analysis and leakage current of memory design is increasing. This paper describes about the 1 KB size memory design using SRAM. The proposed design of 8T SRAM single cell in implemented in array structure of size 32x32.The design structure reduces the power by 75% by reducing the leakage current. The proposed 8T SRAM cell is implemented and analyzed in 90nm technology using Digital schematic and Micro wind software. 

scholarly journals A Study of Different SRAM Cell Designs

2021 ◽  
Vol 9 (3) ◽  
pp. 303-309
Keyword(s):  
Leakage Current ◽  
Random Access ◽  
Leakage Power ◽  
Static Random Access Memory ◽  
Portable Devices ◽  
Access Memory ◽  
Cell Parameters ◽  
The Past ◽  
Sram Cell ◽  
Power Leakage

Presently, huge advancements are being witnessed in the electronics sector like AR, AI, driverless cars, smart homes, portable devices like mobile phones, etc. that requires the improvement of memory technology for efficient working. Memory plays a major role in the present scenario of improvements and growth. Out of different forms of memory devices, the most popular and presently used type of form is the semiconductor MOS memory, specifically SRAM (Static Random-Access Memory) that plays a very important role in the microprocessor domain as it covers a large portion of the chip. But with the increased scale of integration, leakage power, leakage current, and delay becomes a problem in the designing of an SRAM cell. This paper is a review of SRAM cells that have been proposed in the past for achieving improvement in SRAM cell parameters like power consumption, delay, leakage current, read and write stability, better cell operations, etc.

scholarly journals Improved Device Distribution in High-Performance SiNx Resistive Random Access Memory via Arsenic Ion Implantation

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1401
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko
Keyword(s):  
High Performance ◽  
Conduction Mechanism ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Switching Behavior ◽  
Access Memory ◽  
Current Voltage ◽  
Current Voltage Characteristics ◽  
Limited Conduction

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

scholarly journals Overview of radiation effects on emerging non-volatile memory technologies

2017 ◽  
Vol 32 (4) ◽  
pp. 381-392
Author(s):  
Irfan Fetahovic ◽  
Edin Dolicanin ◽  
Djordje Lazarevic ◽  
Boris Loncar
Keyword(s):  
Radiation Effects ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
High Radiation ◽  
Different Types ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Change Memory

In this paper we give an overview of radiation effects in emergent, non-volatile memory technologies. Investigations into radiation hardness of resistive random access memory, ferroelectric random access memory, magneto-resistive random access memory, and phase change memory are presented in cases where these memory devices were subjected to different types of radiation. The obtained results proved high radiation tolerance of studied devices making them good candidates for application in radiation-intensive environments.

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