scholarly journals A Study of Different SRAM Cell Designs

2021 ◽  
Vol 9 (3) ◽  
pp. 303-309
Keyword(s):  
Leakage Current ◽  
Random Access ◽  
Leakage Power ◽  
Static Random Access Memory ◽  
Portable Devices ◽  
Access Memory ◽  
Cell Parameters ◽  
The Past ◽  
Sram Cell ◽  
Power Leakage

Presently, huge advancements are being witnessed in the electronics sector like AR, AI, driverless cars, smart homes, portable devices like mobile phones, etc. that requires the improvement of memory technology for efficient working. Memory plays a major role in the present scenario of improvements and growth. Out of different forms of memory devices, the most popular and presently used type of form is the semiconductor MOS memory, specifically SRAM (Static Random-Access Memory) that plays a very important role in the microprocessor domain as it covers a large portion of the chip. But with the increased scale of integration, leakage power, leakage current, and delay becomes a problem in the designing of an SRAM cell. This paper is a review of SRAM cells that have been proposed in the past for achieving improvement in SRAM cell parameters like power consumption, delay, leakage current, read and write stability, better cell operations, etc.

scholarly journals KLECTOR: Design of Low Power Static Random-Access Memory Architecture with reduced Leakage Current

2021 ◽  
Author(s):  
Ananth Kumar Tamilarasan ◽  
Darwin Sundarapandi Edward ◽  
Arun Samuel Thankamony Sarasam
Keyword(s):  
Leakage Current ◽  
Random Access ◽  
Static Random Access Memory ◽  
Memory Architecture ◽  
Access Memory ◽  
Leakage Currents ◽  
Output Node ◽  
Voltage Drops ◽  
Novel Approach ◽  
Standby Mode

Abstract A novel approach called Keeper in LEakage Control Transistor (KLECTOR) is presented in this paper to reduce leakage currents in SRAM architecture. The SRAM is significantly affected by the leakage current during the "standby mode", which is caused by the fabric which has a lower threshold voltage. KLECTOR circuit employs less power consumption by restricting the flow of current through devices of less voltage drops and relies heavily on the self-controlled transistor at the output node. It has been found from the presented results that static (leakage) power in the write operation is reduced to 63% and 69 % for the read operation. This proposed approach is designed and simulated using the Virtuoso, Cadence EDA tool.

Design of a Stable Low Power 11-T Static Random Access Memory Cell

2020 ◽  
Vol 29 (13) ◽  
pp. 2050206 ◽  
Author(s):  
Ashish Sachdeva ◽  
V. K. Tomar
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Signal To Noise ◽  
Access Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Variation Tolerance ◽  
Read Signal

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by [Formula: see text] and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology.

A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

2019 ◽  
Vol 29 (05) ◽  
pp. 2050067
Author(s):  
S. R. Mansore ◽  
R. S. Gamad ◽  
D. K. Mishra
Keyword(s):  
High Performance ◽  
Model Simulation ◽  
Random Access ◽  
Leakage Power ◽  
Access Memory ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Operation Characteristics ◽  
Static Noise

Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.

scholarly journals Design, Modeling of Ga-As based MESFET for SRAM Cell

2020 ◽  
Vol 2 (2) ◽  
pp. 86-89
Author(s):  
Manvinder Sharma ◽  
Anuj Kumar Gupta ◽  
Dishant Khosla ◽  
Jagbir Singh Gill ◽  
Hauwa Amshi
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Temperature Tolerance ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Main Attention ◽  
Sram Cell ◽  
Conventional Cell ◽  
Result Analysis ◽  
Reduced Power Consumption

The main attention in the area of technology is given to the low power SRAM (Static random Access Memory).GaAs SRAM have been developed with great efforts which include its many advantages such as reduced power consumption and temperature tolerance. There are many limitations of conventional cell which are overcome by the design of new cell which is used to simulate SRAM. The structure of MESFET and the limitations are discussed in the paper. Further, a code in silvaco is run and simulated and the result analysis is done using tony plots.

scholarly journals VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY

2011 ◽  
Vol 12 (1) ◽  
pp. 13-30 ◽  
Author(s):  
Aminul Islam ◽  
Mohd. Hasan
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Static Random Access Memory ◽  
Access Time ◽  
Access Memory ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Pvt Variations ◽  
Static Noise

This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. The 7T SRAM cell consumes higher hold power due to its extra cell area required for its functionality constraint. It shows 60% improvement in static noise margin (SNM), 71.4% improvement in read static noise margin (RSNM) and 50% improvement in write static noise margin (WSNM). The 6T cell outperforms 7T cell in terms of read access time (TRA) by 13.1%. The write access time (TWA) of 7T cell for writing "1" is 16.6 x longer than that of 6T cell. The 6T cell proves it robustness against PVT variations by exhibiting narrower spread in TRA (by 1.2 x) and Twa (by 3.4x). The 7T cell offers 65.6% saving in read power (RPWR) and 89% saving in write power (WPWR). The RPWR variability indicates that 6T ell is more robust against process variation by 3.9x. The 7T cell shows 1.3x wider write power (WPWR) variability indicating 6T cell's robustness against PVT variations. All the results are based on HSPICE simulation using 32 nm CMOS Berkeley Predictive Technology Model (BPTM).

A Novel Design of High Performance and Robust Ultra-Low Power SRAM Cell Based on Memcapacitor

2021 ◽  
Author(s):  
Alireza Abbasi ◽  
Farbod Setoudeh ◽  
Mohammad Bagher Tavakoli ◽  
Ashkan Horri
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Random Access ◽  
Access Memory ◽  
Ultra Low Power ◽  
Cell Parameters ◽  
Consumption Data ◽  
Sram Cell ◽  
Non Volatile Memory ◽  
Novel Design

Abstract The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.

scholarly journals Circuit Implementation, Operation, and Simulation of Multivalued Nonvolatile Static Random Access Memory Using a Resistivity Change Device

2013 ◽  
Vol 2013 ◽  
pp. 1-9
Author(s):  
Kazuya Nakayama ◽  
Akio Kitagawa
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Power Supply Voltage ◽  
Sram Cell ◽  
Variation Tolerance ◽  
Recall Operation

We proposed and computationally analyzed a multivalued, nonvolatile SRAM using a ReRAM. Two reference resistors and a programmable resistor are connected to the storage nodes of a standard SRAM cell. The proposed 9T3R MNV-SRAM cell can store 2 bits of memory. In the storing operation, the recall operation and the successive decision operation of whether or not write pulse is required can be performed simultaneously. Therefore, the duration of the decision operation and the circuit are not required when using the proposed scheme. In order to realize a stable recall operation, a certain current (or voltage) is applied to the cell before the power supply is turned on. To investigate the process variation tolerance and the accuracy of programmed resistance, we simulated the effect of variations in the width of the transistor of the proposed MNV-SRAM cell, the resistance of the programmable resistor, and the power supply voltage with 180 nm 3.3 V CMOS HSPICE device models.

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