Impact of driver size and interwire parasitics on crosstalk noise and delay

2014 ◽  
Vol 12 (4) ◽  
pp. 475-490
Author(s):  
Devendra Kumar Sharma ◽  
Brajesh Kumar Kaushik ◽  
R.K. Sharma
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Propagation Delay ◽  
Combined Effects ◽  
Crosstalk Noise ◽  
Content Type ◽  
Coupling Capacitance ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Coupling Parasitics

Purpose – The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay. Design/methodology/approach – The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node. Findings – This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out. Originality/value – The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.

A novel MRTD model for signal integrity analysis of resistive driven coupled copper interconnects

2018 ◽  
Vol 37 (1) ◽  
pp. 189-207
Author(s):  
Shashank Rebelli ◽  
Bheema Rao Nistala
Keyword(s):  
Time Domain ◽  
Integrated Circuit ◽  
Signal Integrity ◽  
Propagation Delay ◽  
Average Error ◽  
Crosstalk Noise ◽  
Content Type ◽  
Proposed Model ◽  
On Chip ◽  
Coupling Parasitics

Purpose This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method. Design/methodology/approach The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed. Findings The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage. Practical implications Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab. Originality/value The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.

scholarly journals Vlsi Interconnection Modelling Using a Finite Element Approach

1995 ◽  
Vol 18 (3) ◽  
pp. 179-202
Author(s):  
Umesh Kumar
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Low Complexity ◽  
Stratified Medium ◽  
Base Function ◽  
Large Scale Integration ◽  
Element Approach ◽  
Scale Integration ◽  
High Degree ◽  
Important Shift

In the last decade, an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuit packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. An efficient method is presented to model the parasitic capacitance of VLSI (very large scale integration) interconnections. It is valid for conductors in a stratified medium, which is considered to be a good approximation for theSi−SiO2system of which present day ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a “spider” of edges. Here the method used [1] has very low complexity, as compared to other models used previously [2], and achieves a high degree of precision within the range of validity of the stratified medium.

scholarly journals Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

2021 ◽  
Vol 9 (VI) ◽  
pp. 962-966
Author(s):  
Ayush Tiwari
Keyword(s):  
Large Scale ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Time Duration ◽  
Leakage Reduction ◽  
Large Scale Integration ◽  
Cmos Vlsi ◽  
Scale Integration

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

scholarly journals Unbalanced-Tests to the Improvement of Yield and Quality

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 3032
Author(s):  
Chung-Huang Yeh ◽  
Jwu-E Chen
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Manufacturing Industry ◽  
Product Distribution ◽  
Test Method ◽  
Distribution Model ◽  
Threshold Test ◽  
Yield And Quality ◽  
Large Scale Integration ◽  
Scale Integration

An integrated-circuit testing model (DITM) is used to describe various factors that affect test yield during a test process. We used a probability distribution model to evaluate test yield and quality and introduced a threshold test and a guardband test. As a result of the development speed of the semiconductor manufacturing industry in the future being unpredictable, we use electrical properties of existing products and the current manufacturing technology to estimate future product-distribution trends. In the development of very-large-scale integration (VLSI) testing, the progress of testing technology is very slow. To improve product testing yield and quality, we change the test method and propose an unbalanced-test method, leading to improvements in test results. The calculation using our proposed model and data estimated by the product published by the IEEE International Roadmap for Devices and Systems (IRDS, 2017) proves that the proposed unbalanced-test method can greatly improve test yield and quality and achieve the goal of high-quality, near-zero-defect products.

Regional issues frustrate Nairobi’s foreign strategy

2017 ◽  
Keyword(s):  
Regional Integration ◽  
Foreign Relations ◽  
Large Scale ◽  
Hydrocarbon Exploration ◽  
Regional Security ◽  
Content Type ◽  
Large Scale Integration ◽  
Fatal Attack ◽  
Scale Integration ◽  
The Military

Significance The trip comes shortly after the International Court of Justice (ICJ) ruled that Somalia can pursue a claim against Kenya over a maritime boundary dispute. The ruling was the latest in a series of foreign relations defeats that have called into question the effectiveness of President Uhuru Kenyatta’s foreign policy. Kenya focuses on building regional support for its military action in Somalia and promoting regional integration through large-scale integration projects, while diversifying its portfolio of international partners and marshalling African criticism of perceived Western hypocrisy. However, a series of challenges, including a fatal attack on the military in Somalia and failure to secure the chair of the African Union (AU) Commission, have undermined confidence in the competence of the Kenyatta government on the international stage. Impacts Fears about corruption and political instability discourage regional neighbours from implementing touted infrastructure plans. Kenya will vigorously pursue the maritime border case as it has already granted hydrocarbon exploration and exploitation rights. Regional security considerations may shift as the military effort in Somalia winds down.

Design of bilayer graphene nanoribbon tunnel field effect transistor

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ramesh Kumar Vobulapuram ◽  
Javid Basha Shaik ◽  
Venkatramana P. ◽  
Durga Prasad Mekala ◽  
Ujwala Lingayath
Keyword(s):  
Field Effect ◽  
Large Scale ◽  
Field Effect Transistor ◽  
Graphene Nanoribbons ◽  
Content Type ◽  
Large Scale Integration ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
A New Technique ◽  
Scale Integration

Purpose The purpose of this paper is to design novel tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs). Design/methodology/approach To design the proposed TFET, the bilayer GNRs (BLGNRs) have been used as the channel material. The BLGNR-TFET is designed in QuantumATK, depending on 2-D Poisson’s equation and non-equilibrium Green’s function (NEGF) formalism. Findings The performance of the proposed BLGNR-TFET is investigated in terms of current and voltage (I-V) characteristics and transconductance. Moreover, the proposed device performance is compared with the monolayer GNR-TFET (MLGNR-TFET). From the simulation results, it is investigated that the BLGNR-TFET shows high current and gain over the MLGNR-TFET. Originality/value This paper presents a new technique to design GNR-based TFET for future low power very large-scale integration (VLSI) devices.

scholarly journals PERANCANGAN MULTIPLIER SEKUENSIAL 8-BIT DENGAN TEKNOLOGI 180NM MENGGUNAKAN PERANGKAT LUNAK ELECTRIC

TRANSIENT ◽  
2017 ◽  
Vol 6 (3) ◽  
pp. 476
Author(s):  
Brama Yoga Satria ◽  
Munawar Agus Riyadi ◽  
Muhammad Arfan
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Very Large Scale Integration ◽  
Shift Register ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Logic Unit

Very Large Scale Integration (VLSI) merupakan proses dari pembuatan sirkuit terpadu atau Integrated Circuit (IC) dengan cara menggabungkan ribuan rangkaian berbasis transistor ke dalam sebuah chip atau prosesor. Dengan adanya VLSI, ukuran dari devais elektronik berbasis transistor dapat dimampatkan agar menghemat area, biaya produksi, dan efek parasitik. Prosesor terdiri dari beberapa blok utama sebagai penunjang kerjanya, salah satu blok yang paling penting yaitu Arithmatic  Logic Unit (ALU). Salah satu contoh dari ALU sendiri yaitu adalah multiplier. Multiplier sangat penting untuk banyak dasar proses dari sebuah prosesor. Tujuan dari penelitian ini adalah merancang sebuah multiplier sekuensial 8-bit dengan teknologi 180nm. Multiplier dirancang dengan menggabungkan blok-blok pembangun seperti blok counter, adder, shift register, dan lain-lainnya. Penelitian ini menggunakan perangkat lunak electric untuk mendesain layout dan perangkat lunak LT-Spice untuk menguji fungsional, delay, dan kinerja dari hasil ekstraksi layout. Hasil perancangan ini secara fungsional telah berjalan dengan baik. Multiplier yang dirancang memiliki layout sebesar 3.725.150 lambda2 dengan nilai delay sebesar 4,428ns. Selain itu, frekuensi maksimum yang digunakan untuk mendapatkan hasil yang benar dari multiplier sekuensial 8-bit yaitu 50MHz.

An Approach to Reading Machine Design

1978 ◽  
Vol 20 (3) ◽  
pp. 287-293 ◽  
Author(s):  
Jonathan Allen
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Read Aloud ◽  
Machine Design ◽  
Current Status ◽  
Text To Speech ◽  
Short Term ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Circuit Technology

Within two years, both the required algorithmic competence and the necessary integrated circuit technology will have been developed to a point where practical personal reading machines for the blind will be possible. In this paper, the linguistic and phonetic principles needed to convert optically recognized text to speech are discussed, and it is shown how they mirror the human cognitive ability to read aloud. A perspective on the current status and rate of progress of large scale integration technology is then used to show that economical implementations of even complex text-to-speech algorithms can be realized in the short-term future. Finally, a view of important human factors problems requiring attention is given.

Silicide Applications In Microelectronics

1981 ◽  
Vol 10 ◽  
Author(s):  
Billy L. Crowder
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Large Scale ◽  
Field Effect Transistor ◽  
Oxide Semiconductor ◽  
Device Structures ◽  
Direct Replacement ◽  
Large Scale Integration ◽  
Effect Transistor ◽  
Scale Integration

ABSTRACTThe advent of very-large-scale integration in microelectronics has been achieved by reduction in lithographic dimensions coupled with a corresponding decrease in vertical dimensions in properly scaled device structures. This development has placed severe demands upon interconnection technology. The practice of using semiconducting regions (diffusions or polycrystalline silicon) for interconnecting devices is no longer viable because of the high resistance associated with such regions (i.e. interconnections do not “scale” properly). One solution to this problem is the use of multilevel metallization, but this requires tens of thousands of small contacts to shallow diffusions. Refractory metals such as titanium are being explored as materials which provide the necessary stable low resistance contacts suitable for integrated circuit applications. Another solution to the problem is to develop a higher conductivity material to replace or supplement polycrystalline silicon. Refractory metal disilicides have been extensively investigated for this application -both as a direct replacement for polycrystalline silicon or in a silicide/polycrystalline silicon composite (polycide). A critical review of the present status in both these areas will be presented. Emphasis will be upon our experience gained in conjunction with the development of a 1 μm silicon gate metal/oxide/ semiconductor field effect transistor technology.

The Integration on Electrical Control Systems Based on Optimized Method

2012 ◽  
Vol 490-495 ◽  
pp. 2604-2608
Author(s):  
Ai Rong Zhang
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Vlsi Design ◽  
Hardware Architecture ◽  
Logic Device ◽  
Integrated Circuit Design ◽  
Large Scale Integration ◽  
Hardware Description ◽  
Description Languages ◽  
Scale Integration

Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.

Sign in / Sign up

Export Citation Format

Share Document