Highly cost effective and high performance 65nm S/sup 3/ ( stacked single-crystal Si) SRAM technology with 25f 2 , 0.16μm/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

2005 ◽  
Author(s):  
Soon-Moon Jung ◽  
Y. Rah ◽  
Taehong Ha ◽  
Hanbyung Park ◽  
Chulsoon Chang ◽  
...  
Keyword(s):  
Single Crystal ◽  
High Speed ◽  
High Performance ◽  
Cost Effective ◽  
High Density

scholarly journals Polycrystalline SnSe with a thermoelectric figure of merit greater than the single crystal

2021 ◽  
Author(s):  
Chongjian Zhou ◽  
Yong Kyu Lee ◽  
Yuan Yu ◽  
Sejin Byun ◽  
Zhong-Zhen Luo ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Single Crystal ◽  
High Performance ◽  
Figure Of Merit ◽  
Waste Heat ◽  
Electric Energy ◽  
Cost Effective ◽  
Tin Selenide ◽  
Tin Oxides ◽  
Thermally Conductive

AbstractThermoelectric materials generate electric energy from waste heat, with conversion efficiency governed by the dimensionless figure of merit, ZT. Single-crystal tin selenide (SnSe) was discovered to exhibit a high ZT of roughly 2.2–2.6 at 913 K, but more practical and deployable polycrystal versions of the same compound suffer from much poorer overall ZT, thereby thwarting prospects for cost-effective lead-free thermoelectrics. The poor polycrystal bulk performance is attributed to traces of tin oxides covering the surface of SnSe powders, which increases thermal conductivity, reduces electrical conductivity and thereby reduces ZT. Here, we report that hole-doped SnSe polycrystalline samples with reagents carefully purified and tin oxides removed exhibit an ZT of roughly 3.1 at 783 K. Its lattice thermal conductivity is ultralow at roughly 0.07 W m–1 K–1 at 783 K, lower than the single crystals. The path to ultrahigh thermoelectric performance in polycrystalline samples is the proper removal of the deleterious thermally conductive oxides from the surface of SnSe grains. These results could open an era of high-performance practical thermoelectrics from this high-performance material.

scholarly journals High-speed high-resolution laser diode-based photoacoustic microscopy for in vivo microvasculature imaging

2021 ◽  
Vol 4 (1) ◽  
Author(s):  
Xiufeng Li ◽  
Victor T C Tsang ◽  
Lei Kang ◽  
Yan Zhang ◽  
Terence T W Wong
Keyword(s):  
High Resolution ◽  
High Speed ◽  
High Performance ◽  
Continuous Wave ◽  
Signal To Noise Ratio ◽  
Cost Effective ◽  
High Signal ◽  
Photoacoustic Microscopy ◽  
Mouse Ear

AbstractLaser diodes (LDs) have been considered as cost-effective and compact excitation sources to overcome the requirement of costly and bulky pulsed laser sources that are commonly used in photoacoustic microscopy (PAM). However, the spatial resolution and/or imaging speed of previously reported LD-based PAM systems have not been optimized simultaneously. In this paper, we developed a high-speed and high-resolution LD-based PAM system using a continuous wave LD, operating at a pulsed mode, with a repetition rate of 30 kHz, as an excitation source. A hybrid scanning mechanism that synchronizes a one-dimensional galvanometer mirror and a two-dimensional motorized stage is applied to achieve a fast imaging capability without signal averaging due to the high signal-to-noise ratio. By optimizing the optical system, a high lateral resolution of 4.8 μm has been achieved. In vivo microvasculature imaging of a mouse ear has been demonstrated to show the high performance of our LD-based PAM system.

scholarly journals A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-Via and Solder Bumping Process

Metals ◽  
2021 ◽  
Vol 11 (10) ◽  
pp. 1664
Author(s):  
Do Hoon Cho ◽  
Seong Min Seo ◽  
Jang Baeg Kim ◽  
Sri Harini Rajendran ◽  
Jae Pil Jung
Keyword(s):  
High Speed ◽  
High Performance ◽  
New Technologies ◽  
Three Dimensional ◽  
High Density ◽  
Internal Stresses ◽  
Deep Reactive Ion Etching ◽  
Fifth Generation ◽  
Precise Understanding ◽  
Fabrication Defects

With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

HIGH PERFORMANCE ECL-BiCMOS TECHNOLOGY

1993 ◽  
Vol 04 (03) ◽  
pp. 283-299
Author(s):  
T. M. LIU ◽  
R. G. SWARTZ ◽  
T.Y. CHIU
Keyword(s):  
High Speed ◽  
High Performance ◽  
Process Integration ◽  
High Density ◽  
Bipolar Devices ◽  
Bipolar Technology ◽  
Bicmos Technology ◽  
Bipolar Circuit

With the increasing maturity of conventional Bipolar-CMOS (BiCMOS) technologies, a new category of BiCMOS called "ECL-BiCMOS" or high performance BiCMOS technology has emerged. These ECL-BiCMOS technologies offer not only high density CMOS capability, but also feature high speed bipolar devices for emitter couple logic (ECL) and mixed analog/digital applications. Since many process requirements of advanced bipolar technology differ from those of CMOS, to fabricate high speed bipolar devices without compromising CMOS performance is the primary challenge. In this paper, we discuss key process integration issues and review various approaches. In particular, we describe a recently developed half-micron super self-aligned BiCMOS technology. Together with high density/high speed CMOS, multi-GHz communication bipolar circuit results are presented to show the potential of high performance BiCMOS technology.

Design and Analysis of Rotary Positive Displacement Mechanism for Oil-Less Compression

2010 ◽  
Author(s):  
Holger Roser
Keyword(s):  
High Speed ◽  
High Performance ◽  
Effective Means ◽  
Cost Effective ◽  
Industrial Applications ◽  
Two Phase ◽  
Major Drawback ◽  
Displacement Mechanism ◽  
Flow Losses ◽  
Positive Displacement

In this paper, a simple positive displacement mechanism is investigated, which comprises two counter-rotating meshing rotors within a casing. Although considered for various applications more than a century ago, the basic geometry of this mechanism has not been further explored or adapted to modern gas compressor technology. As a fully balanced rotational mechanism operating at uniform angular velocity, potential applications range from pumps to expanders, from slow large displacement to high-speed devices; nonetheless, this research focuses on high-performance oil-less gas compressors as an ideal application. During one complete cycle, the main rotor compresses and discharges the fluid, whilst the secondary rotor seals the compression chamber. Important features of this mechanism are the circular profiles of the rotors, the potential to accommodate large ports for reduced flow losses, and ease of cooling. The simple geometry facilitates a cost-effective means of achieving tight operating clearances between rotors and casing for enhanced sealing without the need for liquid lubricants such as oil. This study and preliminary tests indicate that pressure ratios suitable for standard industrial applications can be obtained over a broad speed range, whilst minimizing friction and flow losses, a major drawback of current technologies. Moreover, two-phase compression and injection of liquids prior to compression have been studied and identified as a means to further improve efficiency and cooling.

High-speed High-density Cost-effective Cu-filled Through-Glass-Via Channel for Heterogeneous Chip Integration

2019 ◽  
Author(s):  
Hiroshi Kudo ◽  
Miyuki Akazawa ◽  
Shouhei Yamada ◽  
Masaya Tanaka ◽  
Haruo Iida ◽  
...  
Keyword(s):  
High Speed ◽  
Cost Effective ◽  
High Density

Dual Die Package Design Strategy and Performance

2005 ◽  
Author(s):  
Mahadevan Suryakumar ◽  
Lu-Vong T. Phan ◽  
Mathew Ma ◽  
Wajahat Ahmed
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
High Performance ◽  
Clock Cycle ◽  
Average Power ◽  
Cost Effective ◽  
Design Strategy ◽  
Leakage Power ◽  
Memory Accesses ◽  
And Performance

The alarming growth of power increase has presented numerous packaging challenges for high performance processors. The average power consumed by a processor is the sum of dynamic and leakage power. The dynamic power is proportional to V^2, while the leakage current (therefore leakage power) is proportional to V^b where V is the voltage and b>1 for modern processes. This means lowering voltage reduces energy consumed per clock cycle but reduces the maximum frequency at which the processor can operate at. Since reducing voltage reduces power faster than it does frequency, integrating more cores into the processor would result in better performance/power efficiency but would generate more memory accesses, driving a need for larger cache and high speed signaling [1]. In addition, the design goal to create unified package pinout for both single core and multicore product flavors adds additional constraint to create a cost effective package solution for both market segments. This paper discusses the design strategy and performance of dual die package to optimize package performance for cost.

scholarly journals A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

VLSI Design ◽  
1996 ◽  
Vol 4 (2) ◽  
pp. 119-133 ◽  
Author(s):  
Sungho Kang ◽  
Youngmin Hur ◽  
Stephen A. Szygenda
Keyword(s):  
High Speed ◽  
High Performance ◽  
Fault Simulation ◽  
Cost Effective ◽  
Hardware Accelerator ◽  
Software Simulation ◽  
Simulation Speed ◽  
Array Architecture ◽  
Reconfigurable Array ◽  
Speed Advantage

In order to reduce cost and to achieve high speed a new hardware accelerator for fault simulation has been designed. The architecture of the new accelerator is based on a reconfigurabl mesh type processing element (PE) array. Circuit elements at the same topological level are simulated concurrently, as in a pipelined process. A new parallel simulation algorithm expands all of the gates to two input gates in order to limit the number of faults to two at each gate, so that the faults can be distributed uniformly throughout the PE array. The PE array reconfiguration operation provides a simulation speed advantage by maximizing the use of each PE cell.This new approach provides for a high performance, cost effective, gain over software simulation. Simulation results show that the hardware accelerator is orders of magnitude faster than the software simulation program.

Sign in / Sign up

Export Citation Format

Share Document