scholarly journals A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design

2014 ◽  
Author(s):  
Matheus Trevisan Moreira ◽  
Michel Evandro Arendt ◽  
Ricardo Aquino Guazzelli ◽  
Ney Laert Vilar Calazans
Keyword(s):  
Low Voltage ◽  
Logic Gates ◽  
Null Convention Logic

scholarly journals Graphene-Based Artificial Synapses with Tunable Plasticity

2021 ◽  
Vol 17 (4) ◽  
pp. 1-21
Author(s):  
He Wang ◽  
Nicoleta Cucu Laurenciu ◽  
Yande Jiang ◽  
Sorin Cotofana
Keyword(s):  
Synaptic Plasticity ◽  
Weight Change ◽  
Time Scale ◽  
Large Scale ◽  
Synaptic Weight ◽  
Low Voltage ◽  
Logic Gates ◽  
Full Potential ◽  
Back Gate ◽  
Input Spike

Design and implementation of artificial neuromorphic systems able to provide brain akin computation and/or bio-compatible interfacing ability are crucial for understanding the human brain’s complex functionality and unleashing brain-inspired computation’s full potential. To this end, the realization of energy-efficient, low-area, and bio-compatible artificial synapses, which sustain the signal transmission between neurons, is of particular interest for any large-scale neuromorphic system. Graphene is a prime candidate material with excellent electronic properties, atomic dimensions, and low-energy envelope perspectives, which was already proven effective for logic gates implementations. Furthermore, distinct from any other materials used in current artificial synapse implementations, graphene is biocompatible, which offers perspectives for neural interfaces. In view of this, we investigate the feasibility of graphene-based synapses to emulate various synaptic plasticity behaviors and look into their potential area and energy consumption for large-scale implementations. In this article, we propose a generic graphene-based synapse structure, which can emulate the fundamental synaptic functionalities, i.e., Spike-Timing-Dependent Plasticity (STDP) and Long-Term Plasticity . Additionally, the graphene synapse is programable by means of back-gate bias voltage and can exhibit both excitatory or inhibitory behavior. We investigate its capability to obtain different potentiation/depression time scale for STDP with identical synaptic weight change amplitude when the input spike duration varies. Our simulation results, for various synaptic plasticities, indicate that a maximum 30% synaptic weight change and potentiation/depression time scale range from [-1.5 ms, 1.1 ms to [-32.2 ms, 24.1 ms] are achievable. We further explore the effect of our proposal at the Spiking Neural Network (SNN) level by performing NEST-based simulations of a small SNN implemented with 5 leaky-integrate-and-fire neurons connected via graphene-based synapses. Our experiments indicate that the number of SNN firing events exhibits a strong connection with the synaptic plasticity type, and monotonously varies with respect to the input spike frequency. Moreover, for graphene-based Hebbian STDP and spike duration of 20ms we obtain an SNN behavior relatively similar with the one provided by the same SNN with biological STDP. The proposed graphene-based synapse requires a small area (max. 30 nm 2 ), operates at low voltage (200 mV), and can emulate various plasticity types, which makes it an outstanding candidate for implementing large-scale brain-inspired computation systems.

scholarly journals Analog Low-Voltage Current-Mode Implementation of Digital Logic Gates

2003 ◽  
Vol 26 (2) ◽  
pp. 111-114 ◽  
Author(s):  
Muhammad Taher Abuelma'atti
Keyword(s):  
Power Series ◽  
Low Voltage ◽  
Logic Gates ◽  
Current Mode ◽  
New Technique ◽  
Basic Logic ◽  
Spice Simulation ◽  
Simulation Results ◽  
A New Technique ◽  
Logic Functions

In this letter a new technique is introduced for implementing the basic logic functions using analog current-mode techniques. By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic functions is simplified. Since no transistors are working in saturation, the problem of fan-out is alleviated. To illustrate the proposed technique, a circuit for simultaneous realization of the logic functions NOT, OR, NAND and XOR is considered. SPICE simulation results, obtained with 3 V supply, are included

scholarly journals Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 547-553
Author(s):  
S. M. Rezaul Hasan ◽  
Yufridin Wahab
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Low Voltage ◽  
Logic Gates ◽  
Base Layer ◽  
Cmos Process ◽  
Silicon Area ◽  
Dynamic Power ◽  
Analog Cmos ◽  
Power Delay Product

This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

Improved low voltage dynamic BiCMOS logic gates using output feedthrough

2002 ◽  
Author(s):  
S.M. Rezaul Hasan ◽  
C. Rajagopal ◽  
N. Ula
Keyword(s):  
Low Voltage ◽  
Logic Gates

Synthesis of Low-Voltage Logic Gates on Surrounding Gate SOI CMOS Nanotransistors

2021 ◽  
Vol 23 (2) ◽  
pp. 75-82
Author(s):  
Masalsky N.V. ◽  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Logic Gates ◽  
Active Power ◽  
Short Channel Effects ◽  
Short Channel ◽  
Switching Delay ◽  
Surrounding Gate ◽  
Channel Effects ◽  
Soi Cmos

We discuss the issues of synthesis of low-voltage logic gates on cylindrical surrounding gate SOI CMOS nanotransistors in the supply voltage range up to 0.8 V. In this transistor architecture, it becomes possible to more effectively control the charge in its working area, primarily due to its design parameters. It is also characterized by effective suppression of short-channel effects and a low capacitance value. This leads to a decrease in the level of power dissipation in combination with a reduction in the occupied area. TCAD models of n- and p-types nanotransistors have been developed. The anomalous behavior of the dependence of the threshold voltage on the diameter of the working area is revealed, which is associated with the peculiarities of the manifestation of short-channel effects due to the capacitive interaction of the gate-channel regions and drain-source transitions at small gate lengths. They were used to select prototypes of transistors with optimal parameters for the synthesis of complex logic gates with low supply voltage. Using the mathematical core of the HSPICE program, the dynamic characteristics of the developed physical models of the inverter, the inverter chain, and the XOR2 are numerically investigated. At control voltages of 0.8 V and a frequency of 50 GHz, the inverter model predicts a maximum switching delay of 3.3 ps, a limit level of active power of 1.1 mkW, static 0.3 pW, the XOR2 predicts a maximum switching delay of 8.6 ps, a limit level of active power of 4.9 mkW, static 1.5 pW. The minimum of the product "delay * power" of the adder is at a supply voltage of 0.72 V. Its position does not depend on the set of input signals. At the same time, the maximum switching delay is 10.8 ps, the maximum active power level is 3.9 mkW. The totality of the obtained characteristics allows us to consider the analyzed transistor architecture for creating low-power electronic devices.

Fully depleted SOI CMOS logic gates for low-voltage applications

2008 ◽  
Vol 37 (6) ◽  
pp. 410-417 ◽  
Author(s):  
N. V. Masal’skii
Keyword(s):  
Low Voltage ◽  
Logic Gates ◽  
Fully Depleted ◽  
Soi Cmos

Low-Voltage Low-Power CMOS-Based Current-Mode Implementation of Digital Logic Gates and Combinational Circuits

2021 ◽  
pp. 2150212
Author(s):  
Prabhat Gupta ◽  
Raina Banerjee ◽  
Ravish Sharma
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Geometric Mean ◽  
Series Representation ◽  
Logic Gates ◽  
Current Mode ◽  
Combinational Circuits ◽  
Basic Logic ◽  
Power Circuit ◽  
Logic Functions

In this paper, a new low-voltage low-power circuit is introduced for implementing CMOS-based basic logic functions using the analog current-mode techniques. The logic functions have been realized by using their expansion in Power Series representation, a Squaring circuit and a Geometric Mean circuit. To illustrate the proposed method, simultaneous realization of the basic logic functions NOT, OR, AND, XOR, NOR, NAND and XNOR in a single circuit is considered. Furthermore, these functions have been used to realize various combinational circuits including full-adder, full-subtractor, etc. SPICE simulation results, obtained with 1.5-V supply, are included.

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