PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

2002 ◽  
Author(s):  
B. Maiti ◽  
P.J. Tobin ◽  
C. Hobbs ◽  
R.I. Hegde ◽  
F. Huang ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
Metal Gate ◽  
Fully Depleted ◽  
Tin Metal

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

2009 ◽  
Vol 53 (3) ◽  
pp. 256-265 ◽  
Author(s):  
Rathnamala Rao ◽  
Guruprasad Katti ◽  
Dnyanesh S. Havaldar ◽  
Nandita DasGupta ◽  
Amitava DasGupta
Keyword(s):  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Metal Gate ◽  
Fully Depleted ◽  
Dual Metal ◽  
Threshold Voltage Model

Organic Mask Removal Assessment for 32nm Fully Depleted SOI Technology with TiN-metal Gate on HfO2

2019 ◽  
Vol 16 (5) ◽  
pp. 355-361
Author(s):  
Laurent Lachal ◽  
Julien Chiaroni ◽  
Emile Lajoinie ◽  
Olivier Louveau ◽  
Frederic Ritton ◽  
...  
Keyword(s):  
Metal Gate ◽  
Fully Depleted ◽  
Tin Metal ◽  
Soi Technology

Imaging Performance of aSIL Microscopy on Subsurface Imaging of SOI Chips

2014 ◽  
Author(s):  
Aydan Uyar ◽  
Abdulkadir Yurt ◽  
T. Berkin Cilingiroglu ◽  
Bennett B. Goldberg ◽  
M. Selim Ünlü
Keyword(s):  
Integrated Circuits ◽  
Collection Efficiency ◽  
Numerical Aperture ◽  
Spot Size ◽  
Silicon On Insulator ◽  
Subsurface Imaging ◽  
Bulk Silicon ◽  
Fully Depleted ◽  
Optical Inspection ◽  
Imaging Performance

Abstract The demand for high resolution has raised interest for the use of aplanatic solid immersion lenses (aSIL) for backside optical inspection and failure analysis of integrated circuits due to its high numerical aperture capability. This work investigates the performance of aSIL microscopy in imaging of fully depleted silicon on insulator (SOI) chips and explores the effect of the buried oxide (BOx) thickness on the spatial resolution and photon collection efficiency. Three different cases, namely, bulk silicon, SOI with an ultrathin BOx of 10 nm, and SOI with a standard BOx thickness of 145 nm, are studied. It is observed that there is a 15% drop in the collection efficiency for ultra-thin BOx compared to bulk silicon and up to 80% decrease in the collection efficiency and 30% increase in the spot-size for standard Box.

scholarly journals High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

2020 ◽  
Vol 10 (3) ◽  
pp. 27
Author(s):  
Andrea Ballo ◽  
Alfio Dario Grasso ◽  
Salvatore Pennisi ◽  
Chiara Venezia
Keyword(s):  
Resonant Frequency ◽  
Performance Optimization ◽  
Cmos Technology ◽  
Second Order ◽  
Silicon On Insulator ◽  
Circuit Performance ◽  
Fully Depleted ◽  
Current Consumption ◽  
28 Nm ◽  
Soi Cmos

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

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