Moisture Influence on Reliability and Electrical Characteristics of SiOC:H Low-k Dielectric Material

2019 ◽  
Author(s):  
Matthias Vidal-Dho ◽  
Quentin Hubert ◽  
Patrice Gonon ◽  
Bernard Pelissier ◽  
Pascal Fornara ◽  
...  
Keyword(s):  
Dielectric Material ◽  
Electrical Characteristics ◽  
Moisture Influence ◽  
Low K

The Study of Fluorinated Amorphous Carbon as Low-K Dielectric Material and its Interface with Copper Metallization

1999 ◽  
Vol 565 ◽  
Author(s):  
N. Ariel ◽  
M. Eizenberg ◽  
E. Y. Tzou
Keyword(s):  
Amorphous Carbon ◽  
Nuclear Reactions ◽  
Dielectric Material ◽  
Copper Metallization ◽  
Limiting Factor ◽  
Adhesion Promoter ◽  
Adhesion Promotion ◽  
High Resolution Tem ◽  
Rc Delay ◽  
Low K

AbstractIn order to achieve better performance of devices, the interconnects RC delay time, the limiting factor of the device speed today, must be reduced. This calls for a new interconnect stack: lower resistivity Copper and low k materials (k<3) as dielectrics.Fluorinated amorphous carbon (a-F:C) prepared by HDP- CVD is an attractive candidate as a low-k material. In this work we have studied the film, its stability and its interface with Copper metallization. The high density plasma CVD process resulted in a film which contains C and F at a ratio of 1:0.6 as determined by Nuclear Reactions Analysis. XPS analysis of the Cls transition indicated four types of bonds: C-C, C-CF, CF, and CF2. X-ray diffraction as well as high resolution TEM analyses proved that the film was amorphous at least up to 500°C anneal. For various applications, the advantage of adding a thin bi-layer of a-SiC/SiOx for adhesion promotion purposes was demonstrated. In addition, the interface of a-F:C and the adhesion promoter layer with Ta, TaN and Cu was studied. No interdiffusion was observed by SIMS after 400°C annealing. 500°C annealing caused F outdiffusion from the film and Cu diffusion into the adhesion promoter layer.

Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

2002 ◽  
Vol 716 ◽  
Author(s):  
Ilanit Fisher ◽  
Wayne D. Kaplan ◽  
Moshe Eizenberg ◽  
Michael Nault ◽  
Timothy Weidman
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Hydrogen Plasma ◽  
Porous Silica ◽  
Film Deposition ◽  
Copper Metallization ◽  
High Porosity ◽  
Tem Analysis ◽  
Chip Technology ◽  
Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

Advanced Die Saw Technology for WLCSP Reliability Enhancement

2019 ◽  
Vol 2019 (1) ◽  
pp. 000323-000326
Author(s):  
Ching Chia Chen ◽  
Yu-Po Wang ◽  
Jensen Tsai ◽  
Hsin Long Chen
Keyword(s):  
Plasma Etching ◽  
Dielectric Material ◽  
Side Wall ◽  
Bending Test ◽  
Process Time ◽  
Portable Devices ◽  
Coating Materials ◽  
Reliability Enhancement ◽  
Surrounding Areas ◽  
Low K

Abstract As consumer and portable devices get thinner and more functionality. Chips which are made by less than 28 nm node wafer with extreme Low-k (ELK) inter metal dielectric material is a trend in order to contain more transistors and to lower power consumption. However, side wall crack (SWC) for WLCSP is one of the major challenges since ELK layer getting brittle. Laser grooving is applied to remove metal before blade saw, but the high temperature during laser grooving usually easily generates HAZ (heat-affected zone) which can induce stress concentration and lower chip strength. The laser ablation also leaves metal-silicon residue (or recast) from the re-deposition of silicon to the groove and surrounding areas. Therefore, SWC (sidewall crack) is a huge potential risk waiting to happen after pick and place, during shipment and during SMT process. In the industry, HAZ size and SWC rate could be reduced by adjusting process parameters, or by exploring new alternatives to eliminate HAZ and silicon recast is one of driving factors of this paper. In this study, plasma etching was applied as surface treatment on the scribe line after laser grooving process with ELK wafer. Plasma could etch HAZ and recast area and expected to increase chip strength and reduce SWC rate. Plasma applied with various process time and power, and different types of mask coating materials were studied. Different plasma gases and effectiveness will be discussed. Conventional blade dicing process will be compared to different plasma etching conditions for mechanical properties of die using 3-point bending test to check die strength, and SEM and OM to verify quality of sidewall of the die. Finally drop test was performed to confirm the reliability enhancement.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

scholarly journals Electrical and Reliability Characteristics of Self-Forming Barrier for CuNd/SiOCH Films in Cu Interconnects

Coatings ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 155
Author(s):  
Yi-Lung Cheng ◽  
Chih-Yen Lee ◽  
Wei-Fan Peng ◽  
Giin-Shan Chen ◽  
Jau-Shiung Fang
Keyword(s):  
Dielectric Film ◽  
Alloy Film ◽  
Dielectric Films ◽  
Low Dielectric Constant ◽  
Electrical Characteristics ◽  
Sputtering Deposition ◽  
Cu Interconnects ◽  
Low Dielectric ◽  
Reliability Characteristics ◽  
Low K

In this study, Cu-2.2 at. % Nd alloy films using a co-sputtering deposition method were directly deposited onto porous low-dielectric-constant (low-k) films (SiOCH). The effects of CuNd alloy film on the electrical properties and reliability of porous low-k dielectric films were studied. The electrical characteristics and reliability of the porous low-k dielectric film with CuNd alloy film were enhanced by annealing at 425 °C. The formation of self-forming barrier at the CuNd/SiOCH interface was responsible for this improvement. Therefore, integration with CuNd and porous low-k dielectric is a promising process for advanced Cu interconnects.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

A Novel Polycarbosilane-Based Low-k Dielectric Material

2006 ◽  
Vol 153 (4) ◽  
pp. G267 ◽  
Author(s):  
Pei-I. Wang ◽  
Zhizhong Wu ◽  
Toh-Ming Lu ◽  
Leonard V. Interrante
Keyword(s):  
Dielectric Material ◽  
Low K

STUDY OF COPPER DIFFUSION IN LOW-k THIN FILM USING SIMS

2006 ◽  
Vol 20 (25n27) ◽  
pp. 4165-4170 ◽  
Author(s):  
K. C. AW ◽  
N. T. SALIM ◽  
WEI GAO ◽  
K. PRINCE
Keyword(s):  
Thin Film ◽  
Activation Energy ◽  
Secondary Ion Mass Spectrometry ◽  
Dielectric Material ◽  
Copper Ions ◽  
Dielectric Thin Film ◽  
Copper Diffusion ◽  
Different Temperatures ◽  
Cu Oxidation ◽  
Low K

The aim of this paper is to study Cu diffusion in polymethylsiloxane (LKD-5109) low-k dielectric material manufactured by JSR Micro with respect to applied thermal energy acting alone. Previous study on low-k dielectric thin film uses a combination of electrical and thermal stress to study Cu diffusion producing a combined activation energy. In this paper, a secondary-ion mass spectrometry (SIMS) was used to determine copper diffusion into LKD-5109 thin film on samples baked/annealed at different temperatures ranging from 373K to 573K in forming gas (7% H 2/93% N 2). The results showed that the thermal activation energy (Ea) of Cu thermal diffusion is approximately 0.14eV for baking/annealing temperature ranging from 373K to 523K. The Ea will increase to greater than 0.58eV for temperature above 523K with Cu oxidation. The increase in Ea suggests a transport mechanism due to Cu oxidation where oxidized Cu is a source of copper ions that diffused through the low-k dielectric film.

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