Physics based current and capacitance model of short-channel double gate and gate-all-around MOSFETs

2008 ◽  
Author(s):  
H. Borli ◽  
S. Kolberg ◽  
T. A. Fjeldly
Keyword(s):  
Double Gate ◽  
Short Channel ◽  
Capacitance Model

scholarly journals Effect of radius on various parameters of cylindrical surrounding double-gate (CSDG) MOSFET

2018 ◽  
Vol 7 (4) ◽  
pp. 2127
Author(s):  
Okikioluwa E. Oyedeji ◽  
Viranjay M. Srivastava
Keyword(s):  
Carrier Mobility ◽  
Research Work ◽  
Drain Current ◽  
Double Gate ◽  
Drift Diffusion ◽  
Short Channel ◽  
Channel Effect ◽  
Novel Structure ◽  
Capacitance Model ◽  
Improved Performance

The MOSFET is an integral component of electronics device and scaling the device is continuously in progress. This research work intro-duces a novel structure of the Cylindrical Surrounding Double-Gate (CSDG) MOSFET to improve scaling and to suppress Short Channel Effect (SCE). In order to achieve this improvement, the drift-diffusion components are used to analyze the drain current of the device through the Pao-Sah integral. Then transconductance is derived to indicate an improved performance of the proposed design. The capaci-tance characteristics of this MOSFET is also analyzed through the equivalent capacitance model as well as the analysis of the carrier mobility, in which it has been observed that scaling of the device supports increase in mobility of the charge carrier.  

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

2007 ◽  
Vol 54 (8) ◽  
pp. 1943-1952 ◽  
Author(s):  
A. Tsormpatzoglou ◽  
C.A. Dimitriadis ◽  
R. Clerc ◽  
Q. Rafhay ◽  
G. Pananakakis ◽  
...  
Keyword(s):  
Analytical Modeling ◽  
Double Gate ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects

scholarly journals 3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect

2018 ◽  
Vol 12 (3) ◽  
pp. 1358
Author(s):  
Ameer F. Roslan ◽  
F. Salehuddin ◽  
A.S. M.Zain ◽  
K.E. Kaharudin ◽  
H. Hazura ◽  
...  
Keyword(s):  
Leakage Current ◽  
Electrical Characterization ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
3D Design ◽  
Drive Current ◽  
Minimum Requirement ◽  
Technology Roadmap ◽  
Low Performance

<p>This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</p>

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach

2019 ◽  
Vol 38 (2) ◽  
pp. 815-828
Author(s):  
Ajay Kumar Singh
Keyword(s):  
Poisson’S Equation ◽  
Analytical Models ◽  
Double Gate ◽  
Poisson's Equation ◽  
Short Channel ◽  
Content Type ◽  
Dg Mosfet ◽  
Channel Potential ◽  
Work Functions ◽  
Long Channel

Purpose This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs. Design/methodology/approach This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach. Findings It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement. Originality/value Compact Analytical models for undoped symmetric double gate MOSFETs.

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