scholarly journals Effect of radius on various parameters of cylindrical surrounding double-gate (CSDG) MOSFET

2018 ◽  
Vol 7 (4) ◽  
pp. 2127
Author(s):  
Okikioluwa E. Oyedeji ◽  
Viranjay M. Srivastava
Keyword(s):  
Carrier Mobility ◽  
Research Work ◽  
Drain Current ◽  
Double Gate ◽  
Drift Diffusion ◽  
Short Channel ◽  
Channel Effect ◽  
Novel Structure ◽  
Capacitance Model ◽  
Improved Performance

The MOSFET is an integral component of electronics device and scaling the device is continuously in progress. This research work intro-duces a novel structure of the Cylindrical Surrounding Double-Gate (CSDG) MOSFET to improve scaling and to suppress Short Channel Effect (SCE). In order to achieve this improvement, the drift-diffusion components are used to analyze the drain current of the device through the Pao-Sah integral. Then transconductance is derived to indicate an improved performance of the proposed design. The capaci-tance characteristics of this MOSFET is also analyzed through the equivalent capacitance model as well as the analysis of the carrier mobility, in which it has been observed that scaling of the device supports increase in mobility of the charge carrier.  

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

Ion implantation for low-resistive source/drain contacts in FinFET devices

2008 ◽  
Vol 1070 ◽  
Author(s):  
Mark J. H. van Dal ◽  
Ray Duffy ◽  
Bartek J. Pawlak ◽  
Nadine Collaert ◽  
Malgorzata Jurczak ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Doping Concentration ◽  
Silicon Crystal ◽  
Thin Body ◽  
Device Performance ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effect ◽  
A New Technique ◽  
Resistive Source

ABSTRACTFinFET is one of the leading candidates to replace the classical planar MOSFET for future CMOS technologies due to the double-gate configuration of the device leading to an intrinsically superior short channel effect (SCE) control. A major challenge for FinFETs is the increase in parasitic source-drain resistance (Rsd) as the fin width is scaled. As fins must be narrow in order to control SCEs, Rsd reduction is critical. This work will deal with the challenges faced in the use of ion implantation for the low-ohmic source-drain contacts. Firstly a new technique to characterize fin sidewall doping concentration will be introduced. We will have a closer look at the Rsd dependency upon fin width for different fin implant conditions and investigate how the implant conditions affect FinFET device performance. It will be shown that the cause of the device degradation upon fin width scaling is related to the fundamental issues of silicon crystal integrity in thin-body Si after amorphizing implant and recrystallization during source-drain activation.

Influences of Carrier Transport on Drain-Current Variability of MOSFETs

2011 ◽  
Vol 470 ◽  
pp. 184-187 ◽  
Author(s):  
Kenji Ohmori ◽  
Kenji Shiraishi ◽  
Keisaku Yamada
Keyword(s):  
Carrier Transport ◽  
Drain Current ◽  
Short Channel ◽  
Short Channel Effect ◽  
Conduction Mechanisms ◽  
Channel Effect

We have investigated the static variability of p-MOSFETs by evaluating the drain current under various conditions of gate and drain voltages. The value of drain current variability (σId/Id) is proportional to (LW)-1/2 before the short channel effect appears, being similar to that of Vt variability. The magnitude of σId/Id decreases as the gate overdrive (Vg-Vt) decreases, and it is classified into two regimes that correspond to the carrier conduction mechanisms, namely diffusion and drift transports. This result strongly suggests that the dominant factors for determining σId/Id values are related to the carrier conduction mechanisms.

scholarly journals Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019 ◽  
Vol 8 (2S6) ◽  
pp. 783-791
Keyword(s):  
Field Effect Transistors ◽  
Scaling Limit ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Length Variation ◽  
Gate Length ◽  
Double Gate ◽  
Simulation Design ◽  
Short Channel ◽  
Fully Depleted

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg ) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively

Effects of Compositional Segregation and Short Channel on Threshold Voltage of nMOSFET

1997 ◽  
Vol 490 ◽  
Author(s):  
Julie Y. H. Lee ◽  
Tom C. H. Lee ◽  
Mike Embry ◽  
Keenan Evans ◽  
Dan Koch ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
Channel Length ◽  
Drift Diffusion ◽  
Short Channel ◽  
Short Channel Effect ◽  
Dopant Segregation ◽  
Channel Effect ◽  
Substrate Doping ◽  
Compositional Segregation

ABSTRACTThis study calculates the threshold voltage (VT) roll-off behavior caused by short channel effect (SCE) as a result of scaling and the reverse short-channel effect (RSCE) due to B segregation around source and drain junctions by using the 2D device simulator - SILVACO™-ATLAS. The simulation results are comparable with the experimental data. It suggests that the drift diffusion physics can predict SCE and RSCE very well to sub-0.25μ Si n-MOSFET devices. The modeling results indicate the VT roll off at shorter channel length for devices with higher substrate doping concentration. VT increases if the local p-dopant segregation exists around the source and drain junction. It is observed that RSCE is more significant for devices with lower substrate doping concentration and shorter channel length.

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