Micro-system process for education: morphological and electrical characterization

Author(s):  
L. Palun ◽  
L. Montes ◽  
P. Morfouli ◽  
N. Mathieu ◽  
N. Guillemot ◽  
...  
1981 ◽  
Vol 4 ◽  
Author(s):  
T. J. Stultz ◽  
J. F. Gibbons

ABSTRACTStructural and electrical characterization of laser recrystallized LPCVD silicon films on amorphous substrates using a shaped cw laser beam have been performed. In comparing the results to data obtained using a circular beam, it was found that a significant increase in grain size can be achieved and that the surface morphology of the shaped beam recrystallized material was much smoother. It was also found that whereas circular beam recrystallized material has a random grain structure, shaped beam material is highly oriented with a <100> texture. Finally the electrical characteristics of the recrystallized film were very good when measured in directions parallel to the grain boundaries.


2002 ◽  
Vol 720 ◽  
Author(s):  
Costas G. Fountzoulas ◽  
Daniel M. Potrepka ◽  
Steven C. Tidrow

AbstractFerroelectrics are multicomponent materials with a wealth of interesting and useful properties, such as piezoelectricity. The dielectric constant of the BSTO ferroelectrics can be changed by applying an electric field. Variable dielectric constant results in a change in phase velocity in the device allowing it to be tuned in real time for a particular application. The microstructure of the film influences the electronic properties which in turn influences the performance of the film. Ba0.6Sr0.4Ti1-y(A 3+, B5+)yO3 thin films, of nominal thickness of 0.65 μm, were synthesized initially at substrate temperatures of 400°C, and subsequently annealed to 750°C, on LaAlO3 (100) substrates, previously coated with LaSrCoO conductive buffer layer, using the pulsed laser deposition technique. The microstructural and physical characteristics of the postannealed thin films have been studied using x-ray diffraction, scanning electron microscopy, and nano indentation and are reported. Results of capacitance measurements are used to obtain dielectric constant and tunability in the paraelectric (T>Tc) regime.


2011 ◽  
Vol E94-C (2) ◽  
pp. 157-163 ◽  
Author(s):  
Masakazu MUROYAMA ◽  
Ayako TAJIRI ◽  
Kyoko ICHIDA ◽  
Seiji YOKOKURA ◽  
Kuniaki TANAKA ◽  
...  

Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.


Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.


Author(s):  
Jon C. Lee ◽  
J. H. Chuang

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.


Author(s):  
C.Q. Chen ◽  
P.T. Ng ◽  
G.B. Ang ◽  
Francis Rivai ◽  
S.L. Ting ◽  
...  

Abstract As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically. But sometimes the EFA spot coverage is too big to do nanoprobing analysis. Then further narrow-down is quite critical to identify the suspected structure before nanoprobing is employed. That means there is a gap between global fault isolation and localized device analysis. Under these kinds of situation, PVC and AFP current image are offen options to identify the suspected structure, but they still have their limitation for many soft defect or marginal fails. As in this case, PVC and AFP current image failed to identify the defect in the spot range. To overcome the shortage of PVC and AFP current image analysis, laser was innovatively applied in our current image analysis in this paper. As is known to all, proper wavelength laser can induce the photovoltaic effect in the device. The photovoltaic effect induced photo current can bring with it some information of the device. If this kind of information was properly interpreted, it can give us some clue of the device performance.


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