The impact of the carrier transport on the random dopant induced drain current variation in the saturation regime of advanced strained-silicon CMOS devices

The analytical probabilistic modelling of random variation in the drain current of a Floating-Gate MOSFET (FGMOSFET) induced by manufacturing process variations has been performed. Both triode and saturation region operated FGMOSFETs have been considered. The results have been found to be very efficient since they can accurately fit the probabilistic distributions of normalized random drain current variations of the candidate triode and saturation FGMOSFETs obtained using the 0.25μm level BSIM3v3 based Monte-Carlo SPICE simulations, where the variation of the saturation FGMOSFET has been found to be more severe. These results also satisfy the goodness of fit test at a very high level of confidence and more accurately than the results of the previous probabilistic modelling attempts. Using our results, many statistical parameters, probabilities and the objective functions, which are useful in statistical/variability aware analysis and design involving FGMOSFETs can be formulated. The impact of drain current variation upon the design trade-offs can be studied. It has been found that the occurrence of the drain current variation is absolutely certain. Moreover, the analytical probabilistic modelling and computationally efficient statistical/ variability aware simulation of FGMOSFET based circuits can also be performed.

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The Impact of Spacer Oxide Material on the Underlapped SOI-nFinFET Working as Charged Based Radiation Sensor

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v16i2.461 ◽

2021 ◽

Vol 16 (2) ◽

pp. 1-6

Author(s):

William Da Silva Fonseca ◽

Paula Ghedini Der Agopian

Keyword(s):

Series Resistance ◽

Drain Current ◽

Oxide Material ◽

Electrical Behavior ◽

Radiation Sensor ◽

Current Variation ◽

Fringing Field ◽

Charge Concentration ◽

Low Permittivity ◽

The Impact

In this work, the influence of the underlap region on the electrical behavior of a SOI-nFinFET transistor has been studied with the purpose of radiation sensing. The analysis was performed by evaluating the impact of variations in the underlap region on the on-state current and by studying its sensitivity. The impact of the underlap region on the drain current and, consequently, on the devices’ sensitivity was explained by the analysis of series resistance, the fringing field and electron density. Considering the main impact of radiation in these devices, the study of sensitivity was also performed taking into consideration the variation of oxide trapped charges density. When applying the transistor to a harsh environment, the Underlapped FinFET showed to be a quite respectable radiation sensor, since the results performed with very good sensitivities when using long and narrow spacer oxide with low permittivity oxide. With thicker spacer oxide in the underlap region, the charge concentration makes the spreading field high enough to overcome the series resistance effect, which results in a less sensible device. Once presented the on-state current variation of the Underlapped FinFET, the study turns radiation-sensing purpose applicable using the excellent characteristics of this device, which is shown in detail throughout this work.

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Model of Nonuniform Channel for the Charge Carrier Transport in Nanoscale FETs

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.276.59 ◽

2011 ◽

Vol 276 ◽

pp. 59-65

Author(s):

V.P. Popov ◽

M.A. Ilnitsky

Keyword(s):

Carrier Transport ◽

Narrow Band ◽

Drain Current ◽

Experimental Fact ◽

New Materials ◽

Physical Reason ◽

Mobility Degradation ◽

Modeling Data ◽

Length Scaling ◽

Silicon Cmos

Mobility degradation during gate length scaling is a well established experimental fact, which is confirmed also by Monte –Carlo simulation. We have analyzed the physical reason for this degradation using experimental and modeling data obtained in classic drift-diffusional approximation with electric field dependences of electron mobility. We have shown that this dependence is a main reason for mobility degradation in nanoscale FETs, which means also that the same reason will limit the drain current in future post-silicon CMOS generation with new materials like narrow band III/V compounds or graphene with the highest carrier velocity near 108 cm/s.

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Impact of interface trap charges on Junctionless double and triple metal gate High-k Gate All Around Nanowire FET based Alzheimer Biosensor

10.21203/rs.3.rs-504559/v1 ◽

2021 ◽

Author(s):

Rishu Chaujar ◽

Mekonnen Getnet Yirak

Keyword(s):

Threshold Voltage ◽

Positive Impact ◽

Drain Current ◽

Interface Trap ◽

Metal Gate ◽

High K ◽

Current Threshold ◽

Subthreshold Voltage ◽

Output Characteristics ◽

The Impact

Abstract In this work, junctionless double and triple metal gate high-k gate all around nanowire field-effect transistor-based APTES biosensor has been developed to study the impact of ITCs on device sensitivity. The analytical results were authenticated using ‘‘ATLAS-3D’’ device simulation tool. Effect of different interface trap charge on the output characteristics of double and triple metal gate high-k gate all around junctionless NWFET biosensor was studied. Output characteristics, like transconductance, output conductance,drain current, threshold voltage, subthreshold voltage and switching ratio, including APTES biomolecule, have been studied in both devices. 184% improvement has been investigated in shifting threshold voltage in a triple metal gate compared to a double metal gate when APTES biomolecule immobilizes on the nanogap cavity region under negative ITCs. Based on this finding, drain off-current ratio and shifting threshold voltage were considered as sensing metrics when APTES biomolecule immobilizes in the nanogap cavity under negative ITCs which is significant for Alzheimer's disease detection. We signifies a negative ITC has a positive impact on our proposed biosensor device compared to positive and neutral ITCs.

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Analytical drain current model to study the impact of interface trap charges on device performance of Double Gate Ge Ferroelectric FET (DGGeFeFET)

2018 Conference on Emerging Devices and Smart Systems (ICEDSS) ◽

10.1109/icedss.2018.8544314 ◽

2018 ◽

Author(s):

Monika Bansal ◽

Harsupreet Kaur

Keyword(s):

Current Model ◽

Drain Current ◽

Interface Trap ◽

Device Performance ◽

Double Gate ◽

The Impact ◽

Trap Charges

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Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

10.21203/rs.3.rs-271741/v1 ◽

2021 ◽

Author(s):

SHIKHA U S ◽

Rekha K James ◽

Jobymol Jacob ◽

Anju Pradeep

Keyword(s):

Drain Current ◽

Gate Oxide ◽

Negative Capacitance ◽

Double Gate ◽

High K ◽

Gate Control ◽

Effect Transistor ◽

Dimensional Simulation ◽

The Impact ◽

Low K

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

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Metastable Defect Distributions in CIGS Solar Cells and Their Impact on Device Efficiency

MRS Proceedings ◽

10.1557/proc-1012-y04-01 ◽

2007 ◽

Vol 1012 ◽

Cited By ~ 5

Author(s):

Malgorzata Igalson

Keyword(s):

Carrier Transport ◽

Theoretical Calculations ◽

Electrical Characteristics ◽

Current Voltage ◽

Device Efficiency ◽

Current Voltage Characteristics ◽

Cigs Solar Cells ◽

Metastable Effects ◽

The Impact ◽

Metastable Defect

AbstractMetastabilities in the electrical characteristics of CIGS devices are commonly observed phenomena originating from persistent changes of shallow and deep levels distributions within the absorber. We examine characteristic changes induced by voltage bias and light together with their relaxation behavior and interpret them as the consequences of a negative-U type of centers predicted by theoretical calculations of Lany and Zunger. It is shown how the properties of these centers justify a model of p+ layer explaining specific features of light and dark current-voltage characteristics. The discussion showing the impact of various charge distributions on carrier transport is presented. The arguments are provided, that centers responsible for metastable effects are also to blame for majority of photovoltaic losses exhibited in various devices.

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