Novel Nano-Scale Conductive Films With Enhanced Electrical Performance and Reliability for High Performance Fine Pitch Interconnect

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.

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Nano-scale Conductive Films for High Performance Fine Pitch Interconnect

MRS Proceedings ◽

10.1557/proc-0990-b05-05 ◽

2007 ◽

Vol 990 ◽

Author(s):

Yi Li ◽

Myung Jin Yim ◽

Kyung Sik Moon ◽

ChingPing Wong

Keyword(s):

High Performance ◽

Electrical Conductance ◽

Conductive Adhesives ◽

Bonding Pressure ◽

Nano Scale ◽

Fine Pitch ◽

Conductive Film ◽

Joint Resistance ◽

Conductive Fillers ◽

Free Solder

ABSTRACTIn this paper, a novel nano-scale conductive film which combines the advantages of both traditional anisotropic conductive adhesives/films (ACAs/ACFs) and nonconductive adhesives/films (NCAs/NCFs) is introduced and developed for next generation high performance ultra-fine pitch packaging applications. This novel interconnect film possesses the properties of electrical conduction along the z-direction with relatively low bonding pressure (ACF-like) and the ultra-fine pitch (< 100 nm) capability (NCF-like). Unlike typical ACF which requires 1–5 vol% of conductive fillers, the novel nano-scale conductive film only needs less than 0.1 vol% conductive fillers to achieve good electrical conductance in the z direction. The nano-scale conductive film also allows a lower bonding pressure than NCF to achieve a much lower joint resistance (over two orders of magnitude lower than typical ACF joints) and higher current carrying capability. With low temperature sintering of nano-silver fillers, the joint resistance of the nano-scale conductive film could be as low as 10−5 Ohm, even lower than the NCF and lead-free solder joints. The reliability of the nano-scale conductive film after high temperature and humidity test (85°C/85%RH) was also improved compared to the NCF joints. As such, a high performance, fine pitch conductive film was developed.

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Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2016dpc-tp24 ◽

2016 ◽

Vol 2016 (DPC) ◽

pp. 000809-000825

Author(s):

Bernard Adams ◽

Won Kyung Choi ◽

Duk Ju Na ◽

Andy Yong ◽

Seung Wook Yoon ◽

...

Keyword(s):

Line Width ◽

High Performance ◽

Process Development ◽

Data Access ◽

Electrical Performance ◽

Logic Device ◽

Wafer Level ◽

Component Level ◽

Wafer Level Packaging ◽

Fine Pitch

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. One of the greatest challenges facing wafer level packaging at present is the availability of routing and interconnecting high I/O fine pitch area array. RDL (redistribution layer) allows signal and supply I/O's to be redistributed to a footprint larger than the chip footprint in eWLB . Required line widths and spacing of 2/2 μm for eWLB applications support the bump pitch of less than 40um. Finer line width and spacing are critical for further design flexibility as well as electrical performance improvement. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2um line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

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Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2012dpc-wa14 ◽

2012 ◽

Vol 2012 (DPC) ◽

pp. 001432-001451

Author(s):

Anupam Choubey ◽

E. Anzures ◽

A. Dhoble ◽

D. Fleming ◽

M. Gallagher ◽

...

Keyword(s):

High Performance ◽

Flip Chip ◽

Fatigue Testing ◽

Electrical Performance ◽

Process Time ◽

Wafer Level ◽

Fine Pitch ◽

Semiconductor Packages ◽

Reliability Performance ◽

3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

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Ultra-Uniform and Very Thin Ag Nanowires Synthesized via the Synergy of Cl−, Br− and Fe3+ for Transparent Conductive Films

Nanomaterials ◽

10.3390/nano10020237 ◽

2020 ◽

Vol 10 (2) ◽

pp. 237

Author(s):

Xiao-Ming Wang ◽

Long Chen ◽

Enrico Sowade ◽

Raul D. Rodriguez ◽

Evgeniya Sheremet ◽

...

Keyword(s):

High Performance ◽

Silver Nanowires ◽

Optical Transmittance ◽

Electrical Performance ◽

Transparent Conductive Films ◽

Conductive Films ◽

High Optical Transmittance ◽

Ag Nanowires ◽

Fundamental Research ◽

High Figure

The properties and applications of Ag nanowires (AgNWs) are closely related to their morphology and composition. Therefore, controlling the growth process of AgNWs is of great significance for technological applications and fundamental research. Here, silver nanowires (AgNWs) were synthesized via a typical polyol method with the synergistic effect of Cl−, Br−, and Fe3+ mediated agents. The synergistic impact of these mediated agents was investigated intensively, revealing that trace Fe3+ ions provided selective etching and hindered the strong etching effect from Cl− and Br− ions. Controlling this synergy allowed the obtainment of highly uniform AgNWs with sub-30 nm diameter and an aspect ratio of over 3000. Transparent conductive films (TCFs) based on these AgNWs without any post-treatment showed a very low sheet resistance of 4.7 Ω sq−1, a low haze of 1.08% at a high optical transmittance of 95.2% (at 550 nm), and a high figure of merit (FOM) of 1210. TCFs exhibited a robust electrical performance with almost unchanged resistance after 2500 bending cycles. These excellent high-performance characteristics demonstrate the enormous potential of our AgNWs in the field of flexible and transparent materials.

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High Performance Conductive Adhesives for Lead-Free Interconnects

MRS Proceedings ◽

10.1557/proc-0968-v07-01 ◽

2006 ◽

Vol 968 ◽

Cited By ~ 3

Author(s):

Yi Li ◽

ChingPing Wong

Keyword(s):

High Power ◽

High Performance ◽

High Current Density ◽

High Reliability ◽

Nano Particles ◽

Electrical Performance ◽

Conductive Adhesives ◽

Molecular Monolayers ◽

Fine Pitch ◽

Novel Approach

ABSTRACTTin-lead solder alloys are widely used in the electronic industry. With the recognition of toxicity of lead, however, electrically conductive adhesives (ECAs) have been considered as one of the most promising alternatives of tin-lead solder. While silver is the most widely used conductive fillers for ECA, silver migration has been the major concern for the high power and fine pitch applications. In this paper, a novel approach of using self-assembled monolayers (SAMs) passivation has been introduced to control the silver migration in nano-Ag ECAs. The protection of silver nano particles with SAMs reduced the silver migration dramatically and no migration was observed upon application of high voltages (up to 500 V) due to the formation of surface chelating compounds between the SAM and nano silver fillers. Unlike other migration control approaches which sacrifice electrical performance, the SAM passivated nano Ag fillers also enhanced the electrical conductivity and current carrying capability of adhesive joints significantly due to the improved interfacial properties and high current density of those molecular monolayers. The joint resistance of the SAM incorporated nano-Ag conductive adhesive could be achieved as low as 10−5 Ohm (the contact area is 100 ×100 μm2) and the maximum allowable current was higher than 3500 mA. As such, a fine pitch, high performance, non-migration and high reliability adhesives are developed for potential solder replacement in high voltage, high power device applications.

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Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

International Symposium on Microelectronics ◽

10.4071/isom-2013-tp21 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000235-000235

Author(s):

Zhe Li ◽

Siow Chek Tan ◽

Yee Huan Yew ◽

Pheak Ti Teh ◽

MJ Lee ◽

...

Keyword(s):

High Speed ◽

High Performance ◽

Flip Chip ◽

Low Cost ◽

Electrical Performance ◽

Package Design ◽

Cu Pillar ◽

Fine Pitch ◽

Field Programmable ◽

Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

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Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

NPG Asia Materials ◽

10.1038/s41427-021-00314-y ◽

2021 ◽

Vol 13 (1) ◽

Author(s):

Muhammad Naqi ◽

Kyung Hwan Choi ◽

Hocheon Yoo ◽

Sudong Chae ◽

Bum Jun Kim ◽

...

Keyword(s):

Low Temperature ◽

Field Effect ◽

High Performance ◽

Field Effect Transistors ◽

Optical Measurements ◽

Electrical Performance ◽

Large Area ◽

Nanowire Network ◽

P Type ◽

Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

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