Design guideline for minimum channel length in silicon-on-insulator (SOI) mosfet

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

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An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

Nanoscience &Nanotechnology-Asia ◽

10.2174/2210681208666180820151121 ◽

2019 ◽

Vol 9 (4) ◽

pp. 504-511

Author(s):

Sikha Mishra ◽

Urmila Bhanja ◽

Guru Prasad Mishra

Keyword(s):

Analytical Model ◽

Surface Potential ◽

Threshold Voltage ◽

Silicon On Insulator ◽

Junction Depth ◽

Short Channel ◽

Soi Mosfet ◽

Minimum Surface ◽

Recessed Channel ◽

The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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Subboundary Free Submicronic Devices on Laser-Recrystallized Silicon Oninsulator

MRS Proceedings ◽

10.1557/proc-35-607 ◽

1984 ◽

Vol 35 ◽

Author(s):

A.J. Auberton-Herve ◽

J.P. Joly ◽

J.M. Hode ◽

J.C. Castagna

Keyword(s):

Channel Length ◽

Silicon On Insulator ◽

Ring Oscillator ◽

Mos Transistors ◽

Seed Structure ◽

Leakage Currents ◽

Industrial Processing ◽

Laser Recrystallization ◽

Dynamic Performances ◽

Lateral Epitaxy

ABSTRACTSeeding from bulk silicon (lateral epitaxy) has been used in Ar+ laser recrystallization to achieve subboundary free silicon on insulator areas. On these areas C.MOS devices have been performed using almost entirely the standard processing steps of a bulk micronic C-MOS technology. n -MOS transistors with channel length as small as 0.3 um have shown very small leakage currents. This is attributed especially to the lack of subboundaries. A 40 % increase in the dynamic performances in comparison with equivalent size C-MOS bulk devices has been obtained (93 ps of delay time per stage for a 101 stages ring oscillator with 0.8 μm of channel length). This is the best result presented so far on recrystallized SOI. No special requirements are needed in the lay out of the circuit with the chosen seed structure. Furthermore an industrial processing rate for the laser recrystallization processing has been achieved using an elliptical laser beam, a high scan velocity (30 cm/s) and a 100 μm line to line scan step (a 4' wafer in 4 minutes).

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Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

10.21203/rs.3.rs-621286/v1 ◽

2021 ◽

Author(s):

Deivakani M ◽

Sumithra M.G ◽

Anitha P ◽

Jenopaul P ◽

Priyesh P. Gandhi ◽

...

Keyword(s):

Breakdown Voltage ◽

Impact Ionization ◽

Semiconductor Industry ◽

Silicon Layer ◽

Silicon On Insulator ◽

Physical Models ◽

Oxide Semiconductor ◽

Soi Mosfet ◽

P Type ◽

Conventional Device

Abstract Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

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STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

Jurnal Teknologi ◽

10.11113/jt.v77.6616 ◽

2015 ◽

Vol 77 (21) ◽

Author(s):

M.N.I.A Aziz ◽

F. Salehuddin ◽

A.S.M. Zain ◽

K.E. Kaharudin

Keyword(s):

Thin Film ◽

Electrical Characteristic ◽

Silicon On Insulator ◽

Electrical Characteristics ◽

Short Channel ◽

Doping Density ◽

Soi Mosfet ◽

Buried Oxide ◽

Soi Technology ◽

Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

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Dynamics, Design, and Application of a Silicon-on-Insulator Technology Based Neuron

MRS Advances ◽

10.1557/adv.2018.490 ◽

2018 ◽

Vol 3 (57-58) ◽

pp. 3347-3357

Author(s):

S. Dutta ◽

T. Chavan ◽

S. Shukla ◽

V. Kumar ◽

A. Shukla ◽

...

Keyword(s):

Impact Ionization ◽

Threshold Current ◽

Channel Length ◽

Silicon On Insulator ◽

Floating Body ◽

Classification Problems ◽

Floating Body Effect ◽

Leakage Mechanism ◽

Silicon Based ◽

Length Scaling

Abstract:Spiking Neural Networks propose to mimic nature’s way of recognizing patterns and making decisions in a fuzzy manner. To develop such networks in hardware, a highly manufacturable technology is required. We have proposed a silicon-based leaky integrate and fire (LIF) neuron, on a sufficiently matured 32 nm CMOS silicon-on-insulator (SOI) technology. The floating body effect of the partially depleted (PD) SOI transistor is used to store “holes” generated by impact ionization in the floating body, which performs the “integrate” function. Recombination or equivalent hole loss mimics the “leak” functions. The “hole” storage reduces the source barrier to increase the transistor current. Upon reaching a threshold current level, an external circuit records a “firing” event and resets the SOI MOSFET by draining all the stored holes. In terms of application, the neuron is able to show classification problems with reasonable accuracy. We looked at the effect of scaling experimentally. Channel length scaling reduces voltage for impact ionization and enables sharper impact ionization producing significant designability of the neuron. A circuit equivalence is also demonstrated to understand the dynamics qualitatively. Three distinct regimes are observed during integration based on different hole leakage mechanism.

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Sub-Continuum Simulations of Heat Conduction in Silicon-on-Insulator Transistors

10.1115/imece1999-1061 ◽

1999 ◽

Author(s):

Per G. Sverdrup ◽

Y. Sungtaek Ju ◽

Kenneth E. Goodson

Keyword(s):

Diffusion Equation ◽

Free Path ◽

Temperature Rise ◽

Mean Free Path ◽

Channel Length ◽

Silicon On Insulator ◽

Heat Diffusion ◽

Boltzmann Transport ◽

Heat Diffusion Equation ◽

Silicon Devices

Abstract The temperature rise in compact silicon devices is predicted at present by solving the heat diffusion equation based on Fourier’s law. The validity of this approach needs to be carefully examined for semiconductor devices in which the region of strongest electronphonon coupling is narrower than the phonon mean free path, Λ, and for devices in which Λ is comparable to or exceeds the dimensions of the device. Previous research estimated the effective phonon mean free path in silicon near room temperature to be near 300 nm, which is already comparable with the minimum feature size of current generation transistors. This work numerically integrates the phonon Boltzmann transport equation (BTE) within a two-dimensional Silicon-on-Insulator (SOI) transistor. The BTE is coupled with the classical heat diffusion equation, which is solved in the silicon dioxide layer beneath a transistor with a channel length of 400 nm. The sub-continuum simulations yield a peak temperature rise that is 159 percent larger than predictions using only the classical heat diffusion equation. This work will facilitate the development of simpler calculation strategies, which are appropriate for commercial device simulators.

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Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Journal of Nanotechnology ◽

10.1155/2019/4935073 ◽

2019 ◽

Vol 2019 ◽

pp. 1-12 ◽

Cited By ~ 1

Author(s):

Anjali Priya ◽

Nilesh Anand Srivastava ◽

Ram Awadh Mishra

Keyword(s):

Threshold Voltage ◽

Propagation Delay ◽

Silicon On Insulator ◽

Device Performance ◽

Gate Length ◽

Metal Gate ◽

Short Channel ◽

Fully Depleted ◽

Soi Mosfet ◽

Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

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Reliability challenge of ESD protection: From planner SOI MOSFET to SOI FinFET

Modern Physics Letters B ◽

10.1142/s0217984917400048 ◽

2017 ◽

Vol 31 (19-21) ◽

pp. 1740004 ◽

Cited By ~ 1

Author(s):

Yibo Jiang ◽

Hui Bi ◽

Liangwei Dong ◽

Qinglong Li

Keyword(s):

Electrostatic Discharge ◽

Silicon On Insulator ◽

Heat Conductor ◽

Soi Mosfet ◽

Novel Device ◽

Thermal Distribution ◽

Floating Base ◽

Esd Protection ◽

Tcad Simulation ◽

Soi Technology

Implementation of Electrostatic Discharge (ESD) protection in Silicon on Insulator (SOI) technology is a challenge because of the inherent properties of poor heat conductor and heat trapping. In this paper, a novel device as ESD clamp is proposed as Fix-Base SOI FinFET clamp which addresses the troublesome problem of floating base. Moreover, its manufacturing process is compatible to the normal SOI process flow well. Finally, a detailed discussion including current density and thermal distribution are presented with the technique of 3D TCAD simulation.

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Modeling and Designing a Device Using MuGFETs

ASME 2008 3rd Energy Nanotechnology International Conference ◽

10.1115/enic2008-53015 ◽

2008 ◽

Author(s):

V. K. Lamba ◽

Derick Engles ◽

S. S. Malik

Keyword(s):

Gate Dielectric ◽

Silicon Film ◽

General Rule ◽

Channel Length ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Radius Of Curvature ◽

Short Channel ◽

Dielectric Thickness ◽

Fin Thickness

This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

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