On the Study of Piezoresistive Stress Sensors for Microelectronic Packaging

2000 ◽  
Vol 124 (1) ◽  
pp. 22-26 ◽  
Author(s):  
Ben-Je Lwo ◽  
Ching-Hsing Kao ◽  
Tung-Sheng Chen ◽  
Yao-Shing Chen
Keyword(s):  
Input Power ◽  
Microelectronic Packaging ◽  
Piezoresistive Sensors ◽  
Four Point Bending ◽  
Stress Sensors ◽  
Linear Relationships ◽  
Study Test ◽  
As Stress ◽  
Test Chips ◽  
P Type

Stress measurements in microelectronic packaging through piezoresistive sensors take the advantage of both in-situ and nondestructive. In this study, test chips with both p-type and n-type piezoresistive stress sensors, as well as a heat source, were first designed, then manufactured by a commercialized foundry so that the uniformity of the test chips was expected. Both temperature and stress calibrations were next performed through a special designed MQFP (Metal Quad Flat Package) and four-point bending (4PB) structure, respectively. Measurements of stresses which are produced due to both manufacturing process and thermal effects on the test chips were finally executed, and approximately linear relationships were observed between stress and temperature as well as stress and input power. It is concluded that n-type piezoresistive stress sensors are able to extract stress in microelectronic packaging with good accuracy.

In-Plane Packaging Stress Measurements Through Piezoresistive Sensors

2002 ◽  
Vol 124 (2) ◽  
pp. 115-121 ◽  
Author(s):  
Ben-Je Lwo ◽  
Tung-Sheng Chen ◽  
Ching-Hsing Kao ◽  
Yu-Lin Lin
Keyword(s):  
Thermal Stresses ◽  
Temperature Sensors ◽  
Internal Stresses ◽  
Microelectronic Packaging ◽  
Stress Measurements ◽  
Piezoresistive Sensors ◽  
Stress Sensors ◽  
Induced Stresses ◽  
Packaging Structure ◽  
Test Chips

In our previous works, the piezoresistive sensors have been demonstrated to be accurate and efficient tools for stress measurements in microelectronic packaging. In this study, we first designed test chips with piezoresistive stress sensors, temperature sensors as well as heats, and the test wafers were next manufactured through commercialized IC processes. Piezoresistive sensors on silicon strips, which were cut directly from silicon wafers at a specific angle, were then calibrated, and highly consistent piezoresistive coefficients were extracted at various wafer sites so that both normal and shear stress on the test chips can be measured. Finally, we packaged the test chips into 100-pin PQFP structures with different batches and measured internal stresses on the test chips inside the packaging. After measuring packaging induced stresses as well as thermal stresses on several batches of PQFPs, it was found that the normal stress diversities were obvious from different batches of the packaging structure, and the shearing stresses were approximately zero in all of the PQFPs at different chip site.

Piezoresistive Stress Sensors for Structural Analysis of Electronic Packages

1991 ◽  
Vol 113 (3) ◽  
pp. 203-215 ◽  
Author(s):  
D. A. Bittle ◽  
J. C. Suhling ◽  
R. E. Beaty ◽  
R. C. Jaeger ◽  
R. W. Johnson
Keyword(s):  
Integrated Circuit ◽  
Structural Reliability ◽  
Lattice Structure ◽  
Three Dimensional ◽  
Electronic Packages ◽  
Cubic Symmetry ◽  
Piezoresistive Sensors ◽  
Stress Sensors ◽  
Die Stress ◽  
Test Chips

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the theory of conduction in piezoresistive materials is reviewed and the basic equations applicable to the design of stress sensors on test chips are presented. General expressions are obtained for the stress-induced resistance changes which occur in arbitrarily oriented one-dimensional filamentary conductors fabricated out of crystals with cubic symmetry and diamond lattice structure. These relations are then applied to obtain basic results for stressed in-plane resistors fabricated into the surface of (100) and (111) oriented silicon wafers. Sensor rosettes developed by previous researchers for each of these wafer orientations are reviewed and more powerful rosettes are presented along with the equations needed for their successful application. In particular, a new sensor rosette fabricated on (111) silicon is presented which can measure the complete three-dimensional stress state at points on the surface of a die

Chip-on-Beam and Hydrostatic Calibration of the Piezoresistive Coefficients on (111) Silicon

2007 ◽  
Author(s):  
Chun-Hyung Cho ◽  
Richard C. Jaeger ◽  
Jeffrey C. Suhling ◽  
M. Kaysar Rahim
Keyword(s):  
Pressure Coefficient ◽  
Experimental Methods ◽  
Temperature Dependent ◽  
Pressure Coefficients ◽  
Stress Sensors ◽  
Wide Range ◽  
Complete Set ◽  
Stress Sensing ◽  
Test Chips ◽  
P Type

Stress sensing test chips are used to investigate die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are able to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. Stress sensors fabricated on the surface of the (111) silicon wafers offer the advantage of being able to measure the complete stress state compared to such sensors fabricated on the (100) silicon. However, complete calibration of the three independent piezoresistive coefficients is more difficult and one approach utilizes hydrostatic measurement of the silicon “pressure” coefficients. We are interested in stress measurements over a very broad range of temperatures, and this paper present the experimental methods and results for hydrostatic measurements of the pressure coefficient of both n- and p-type silicon over a wide range of temperatures and then uses the results to provide a complete set of temperature dependent piezoresisitive coefficients for the (111) silicon.

Characterization of the Piezoresistive Coefficients of (100) Silicon From −150 to +125C

2007 ◽  
Author(s):  
Chun-Hyung Cho ◽  
Richard C. Jaeger ◽  
Jeffrey C. Suhling
Keyword(s):  
Integrated Circuit ◽  
Carrier Mobility ◽  
Limited Data ◽  
Experimental Calibration ◽  
Four Point Bending ◽  
Stress Sensors ◽  
Stress Sensing ◽  
Test Chips ◽  
Crystallographic Axes

Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. The test chips incorporate resistor or transistor sensing elements that are able to measure stresses by observing the changes in their resistivity or carrier mobility. This piezoresistive behavior of such sensors is characterized by three piezoresistive coefficients, which are electro-mechanical material constants. We are interested in stress characterization over a very broad range of temperatures. However, the literature provides limited data over the desired range, and even the data at room temperature, exhibit wide discrepancies in magnitude as well as sign. This work focuses on an extensive experimental study of the temperature dependence of the piezoresistive coefficients, π11, π12, and π44, for both p- and n-type silicon. In order to minimize errors associated with misalignment with the crystallographic axes on (100) silicon wafers, anisotropic wet etching was used in this work to accurately locate the axes. A special four-point bending apparatus has been constructed and integrated into an environmental chamber capable of temperatures from −155 to +300°C. Experimental calibration results for the piezoresistive coefficients as a function of temperature from −150°C to +125°C are presented and compared and contrasted with existing values from literature. Measurements were performed using stress sensors fabricated on (100) silicon mounted on PCB material including both die-on-beam and strip-on-beam mounting techniques. Four-point bending (4PB) was used to generate the required stress, and finite element simulations have been used to determine the actual states of stress in the silicon material.

In Situ Chip Stress Extractions for LFBGA Packages Through Piezoresistive Sensors

2009 ◽  
Vol 131 (3) ◽  
Author(s):  
Ben-Je Lwo ◽  
Jeng-Shian Su ◽  
Hsien Chung
Keyword(s):  
Stress Measurements ◽  
Piezoresistive Sensors ◽  
Stress Sensors ◽  
Compressive Stresses ◽  
Fine Pitch ◽  
Low Profile ◽  
Quad Flat Package ◽  
On Chip ◽  
Test Chips

Piezoresistive sensors have been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, test chips with piezoresistive stress sensors, diode temperature sensors as well as heaters were first designed, fabricated, and calibrated. We next packaged the test chips into low profile, fine pitch ball grid array (LFBGA) packaging with 196 balls and measured the stresses on chip surfaces inside the packaging. After measuring the packaging induced stress as well as the stress under stable environmental temperature rises, it was found that compressive stresses were obtained at room temperature, and the stresses were relaxed as temperature went up at a rate between 0.45 MPa/°C and 0.60 MPa/°C. For thermo-stress experiments, the temperatures on chip surfaces at different power levels were measured, and compressive chip stresses were first extracted. As the chip power increased, the compressive stresses became tensions. Since the LFBGA structure is thinner with higher packaging efficiency, different results from our earlier plastic quad flat package stress measurements were observed and discussed. In addition, the final comparisons between the experimental data and the finite element simulations show good consistency.

Investigation of New Geometries for High Duty Cycle Far-Infrared p-Type Germanium Lasers

1999 ◽  
Vol 607 ◽  
Author(s):  
Danielle R. Chamberlin ◽  
Erik Bruendermannw ◽  
Eugene E. Haller
Keyword(s):  
Electric Field ◽  
Duty Cycle ◽  
Pulse Length ◽  
Far Infrared ◽  
Contact Geometry ◽  
Input Power ◽  
High Resistivity ◽  
Field Uniformity ◽  
P Type ◽  
Planar Contact

AbstractWe report on increasing the pulse length and repetition rate of p-type germanium lasers through miniaturization, increased electric field uniformity, and improved cooling. We have recently demonstrated that it is possible to improve the electric field uniformity necessary for an efficient laser and at the same time decrease the electrical input power by using a geometry with d/L>>1, where d is the distance between electrical contacts and L is the length in the direction of the Hall field. In order to achieve good heat sinking along with a large d/L ratio, we have developed a new, planar contact geometry. Attaching an undoped, high-resistivity, single-crystal Si heat sink to the base of the Ge planar contact laser increases the duty cycle by a factor of 5.5. In order to further decrease the input power by decreasing the volume of laser crystals in the planar contact geometry, we show as a proof-of-concept the use of polished strontium titanate single crystals as electrically insulating far-infrared mirrors based on restrahl band reflection. The physical phenomena underlying these improvements in this novel geometry will be discussed.

A study of Cleaning Performance and Mechanisms in Dilute SC-1 Processing

1995 ◽  
Vol 386 ◽  
Author(s):  
P. J. Resnick ◽  
C. L. J. Adkins ◽  
P. J. Clews ◽  
E. V. Thomas ◽  
N. C. Korbe
Keyword(s):  
Elevated Temperatures ◽  
Input Power ◽  
Solution Chemistry ◽  
Dominant Factor ◽  
Surface Model ◽  
Particle Removal ◽  
Post Processing ◽  
Statistical Design Of Experiments ◽  
Ambient Lighting ◽  
P Type

ABSTRACTA statistical design of experiments (DOE) approach has been employed to evaluate the effects of megasonic input power, solution chemistry, bath temperature, and immersion time on particle removal in SC-1 chemistries. Megasonic input power was the dominant factor in the response surface model. Substantially diluted chemistries, performed with high megasonic input power and moderate-to-elevated temperatures. were shown to be very effective for small particle removal. Follow-on studies to the original DOE have led to an investigation of ultradilute SC-1 chemistries with megasonic power. These chemistries ranged from 0 to 1000 ppm of NH4OH and H2O2. Post processing light point defect (LPD) counts differ substantially between bare n and p-type Si<100>, and ambient lighting conditions are shown to influence LPD counts on p-type Si<100>. Solution properties such as pH and oxidation potential have been studied, and an investigation of post processing silicon surface properties is underway.

Evaluation of Alignment Rules Using Stainless Steel Pipes With Non-Aligned Flaws

2009 ◽  
Author(s):  
Kunio Hasegawa ◽  
Katsumasa Miyazaki ◽  
Koichi Saito ◽  
Bostjan Bezensek
Keyword(s):  
Stainless Steel ◽  
Limit Load ◽  
Plastic Collapse ◽  
Paper Briefly ◽  
Limit Loads ◽  
Bending Tests ◽  
Steel Pipes ◽  
Four Point Bending ◽  
Close Proximity ◽  
As Stress

Multiple flaws such as stress corrosion cracks are frequently detected in the same welded lines in pipes. If multiple discrete flaws are in close proximity to one another, alignment rules are used to determine whether the flaws should be treated as non-aligned or as coplanar. Alignment rules are provided in fitness-for-service codes, such as ASME, JSME, API 579, BS 7910, etc. However, the criteria of the alignment rules are different among these codes. This paper briefly introduces these flaw alignment rules, and four-point bending tests performed on stainless steel pipes with two non-aligned flaws. The experimental plastic collapse stresses are determined from the collapse loads and compared with collapse stresses calculated from the limit load criteria. The limit loads are obtained for single non-aligned or aligned coplanar flaws in accordance with the alignment rules. On this basis, the conservatism of the alignment rules in the above codes is assessed.

Measurement of Stress and Delamination in Flip Chip on Laminate Assemblies

2003 ◽  
Author(s):  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
D. Scott Copeland ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Flip Chip ◽  
Acoustic Microscopy ◽  
Valuable Insight ◽  
Stress Distributions ◽  
Environmental Testing ◽  
Stress Measurements ◽  
Piezoresistive Sensors ◽  
Die Stress ◽  
Test Chips ◽  
Stress Variations

Mechanical stress distributions in packaged silicon die that have resulted during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, an overview of recent measurements made in flip chip on laminate assemblies with (111) silicon test chips is presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. The experimental stress measurements in the flip chip samples were then correlated with finite element predictions for the tested configurations. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from −40 to +150°C. Finally the stress variations occurring during thermal cycling from −40 to +125°C have been characterized. These measurements have been correlated with the delaminations occurring at the die passivation to underfill interface measured using C-mode Scanning Acoustic Microscopy (C-SAM). Using the measurements and numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

scholarly journals Microscopic Understanding of the Carrier Transport Process in Ge Nanocrystals Films

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Dan Shan ◽  
Hongyu Wang ◽  
Mingjun Tang ◽  
Jun Xu
Keyword(s):  
Carrier Transport ◽  
Surface States ◽  
Chemical Vapor ◽  
Dark Conductivity ◽  
Linear Relationships ◽  
P Type ◽  
Hydrogenated Amorphous ◽  
Hydrogenated Amorphous Germanium ◽  
Deposited Film ◽  
Ge Nanocrystals

Hydrogenated amorphous germanium (a-Ge:H) films were prepared by a plasma enhanced chemical vapor deposition (PECVD) technique. Ge nanocrystals (Ge NCs) films were obtained by thermal annealing of the as-deposited samples at various temperatures. P-type behavior in Ge NCs films without any external doping was attributed to the holes accumulation caused by acceptor-like surface states. It can be found that the dark conductivity and Hall mobility reached as high as 25.6 S/cm and 182 cm2/V·s in the Ge NCs film annealed at 500°C, which were increased by over four and three orders of magnitude higher than that of the as-deposited film (1.3 × 10-3 S/cm and 0.14 cm2/V·s, resp.). Carrier transport mechanisms of Ge NCs films association with the microstructural characteristics were investigated. Three kinds of temperature-dependent conductivity behaviors, which exhibit the linear relationships of ln⁡σ versus T-1/4, T-1/2, and T-1, respectively, were observed in the temperature regions from 10 K to 500 K, showing different microscopic mechanisms governing carrier transport in Ge NCs film.

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