Characterization of the Piezoresistive Coefficients of (100) Silicon From −150 to +125C

ASME 2007 InterPACK Conference, Volume 2 ◽

10.1115/ipack2007-33053 ◽

2007 ◽

Author(s):

Chun-Hyung Cho ◽

Richard C. Jaeger ◽

Jeffrey C. Suhling

Keyword(s):

Integrated Circuit ◽

Carrier Mobility ◽

Limited Data ◽

Experimental Calibration ◽

Four Point Bending ◽

Stress Sensors ◽

Stress Sensing ◽

Test Chips ◽

Crystallographic Axes

Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. The test chips incorporate resistor or transistor sensing elements that are able to measure stresses by observing the changes in their resistivity or carrier mobility. This piezoresistive behavior of such sensors is characterized by three piezoresistive coefficients, which are electro-mechanical material constants. We are interested in stress characterization over a very broad range of temperatures. However, the literature provides limited data over the desired range, and even the data at room temperature, exhibit wide discrepancies in magnitude as well as sign. This work focuses on an extensive experimental study of the temperature dependence of the piezoresistive coefficients, π11, π12, and π44, for both p- and n-type silicon. In order to minimize errors associated with misalignment with the crystallographic axes on (100) silicon wafers, anisotropic wet etching was used in this work to accurately locate the axes. A special four-point bending apparatus has been constructed and integrated into an environmental chamber capable of temperatures from −155 to +300°C. Experimental calibration results for the piezoresistive coefficients as a function of temperature from −150°C to +125°C are presented and compared and contrasted with existing values from literature. Measurements were performed using stress sensors fabricated on (100) silicon mounted on PCB material including both die-on-beam and strip-on-beam mounting techniques. Four-point bending (4PB) was used to generate the required stress, and finite element simulations have been used to determine the actual states of stress in the silicon material.

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A Compact Eight-terminal Piezotransducer for Stress Measurements in Silicon

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v12i1.447 ◽

2017 ◽

Vol 12 (1) ◽

pp. 24-32

Author(s):

Jose L. Ramirez ◽

Fabiano Fruett

Keyword(s):

Stress State ◽

Integrated Circuits ◽

Carrier Mobility ◽

Structural Integrity ◽

Uniaxial Stress ◽

Silicon Chips ◽

Four Point Bending ◽

Stress Sensing ◽

The Relationship

Deformations in the crystalline structure have an important impact in electric characteristics of the semiconductors, like carrier mobility and concentration. Since mechanical stress and strain are related, an induced stress in silicon chips compromise the performance and structural integrity of Integrated Circuits (ICs). Reason why stress sensing devices are becoming important tools to detect and correct stress related problems, improving the performance and yield of ICs. This work shows the design and characterization of an Eight Terminals Silicon Piezotransduzer (8TSP), a stress sensor device based on the piezoresistive effect and designed to estimate the stress state over the (100) silicon surface. The multi-terminal device integrates a resistor rosette in a single octagonal plate, allowing to change the bias direction and to take measure in different orientations, the relationship between those observations can be used to estimate both direction and magnitude of the stress in a certain area. In order to characterize the device, a four-point-bending apparatus using a circular substrate has to be designed to have control of both magnitude and direction of the applied uniaxial stress. The device was attached to a disk and stress was applied in the main crystallographic directions to observe the piezoresistance characteristics and calibrate the sensor. We applied stress in some other directions and the stress behavior fit the predicted by the theory. Those results confirm that the 8TPS can be used to find the stress state over the surface of a silicon chip.

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Piezoresistive Stress Sensors for Structural Analysis of Electronic Packages

Journal of Electronic Packaging ◽

10.1115/1.2905397 ◽

1991 ◽

Vol 113 (3) ◽

pp. 203-215 ◽

Cited By ~ 155

Author(s):

D. A. Bittle ◽

J. C. Suhling ◽

R. E. Beaty ◽

R. C. Jaeger ◽

R. W. Johnson

Keyword(s):

Integrated Circuit ◽

Structural Reliability ◽

Lattice Structure ◽

Three Dimensional ◽

Electronic Packages ◽

Cubic Symmetry ◽

Piezoresistive Sensors ◽

Stress Sensors ◽

Die Stress ◽

Test Chips

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the theory of conduction in piezoresistive materials is reviewed and the basic equations applicable to the design of stress sensors on test chips are presented. General expressions are obtained for the stress-induced resistance changes which occur in arbitrarily oriented one-dimensional filamentary conductors fabricated out of crystals with cubic symmetry and diamond lattice structure. These relations are then applied to obtain basic results for stressed in-plane resistors fabricated into the surface of (100) and (111) oriented silicon wafers. Sensor rosettes developed by previous researchers for each of these wafer orientations are reviewed and more powerful rosettes are presented along with the equations needed for their successful application. In particular, a new sensor rosette fabricated on (111) silicon is presented which can measure the complete three-dimensional stress state at points on the surface of a die

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Chip-on-Beam and Hydrostatic Calibration of the Piezoresistive Coefficients on (111) Silicon

ASME 2007 InterPACK Conference, Volume 1 ◽

10.1115/ipack2007-33570 ◽

2007 ◽

Author(s):

Chun-Hyung Cho ◽

Richard C. Jaeger ◽

Jeffrey C. Suhling ◽

M. Kaysar Rahim

Keyword(s):

Pressure Coefficient ◽

Experimental Methods ◽

Temperature Dependent ◽

Pressure Coefficients ◽

Stress Sensors ◽

Wide Range ◽

Complete Set ◽

Stress Sensing ◽

Test Chips ◽

P Type

Stress sensing test chips are used to investigate die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are able to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. Stress sensors fabricated on the surface of the (111) silicon wafers offer the advantage of being able to measure the complete stress state compared to such sensors fabricated on the (100) silicon. However, complete calibration of the three independent piezoresistive coefficients is more difficult and one approach utilizes hydrostatic measurement of the silicon “pressure” coefficients. We are interested in stress measurements over a very broad range of temperatures, and this paper present the experimental methods and results for hydrostatic measurements of the pressure coefficient of both n- and p-type silicon over a wide range of temperatures and then uses the results to provide a complete set of temperature dependent piezoresisitive coefficients for the (111) silicon.

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A New Technique for the Characterization of the Adhesion in Integrated Circuit Interconnect Structures

MRS Proceedings ◽

10.1557/proc-863-b1.2 ◽

2005 ◽

Vol 863 ◽

Cited By ~ 1

Author(s):

Ibon Ocana ◽

Jon M. Molina ◽

Diego Gonzalez ◽

M. Reyes Elizalde ◽

Jose M. Sanchez ◽

...

Keyword(s):

Integrated Circuit ◽

Focused Ion Beam ◽

Ion Beam ◽

Two Dimensions ◽

Cross Sectional ◽

Four Point Bending ◽

System A ◽

Patterned Structures ◽

A New Technique

AbstractA new testing technique for the characterization of the mechanical behavior of the interconnect structures of integrated circuit devices is introduced in this paper. Modified crosssectional nanoindentation (MCSN) is the result of extending cross-sectional indentation (CSN) to patterned structures. As in conventional CSN, a Berkovich indenter is used to initiate fracture in the silicon substrate beneath the interconnect structure. The cracks propagate through this structure, preferentially along the weakest interfaces in the system. A FIB (Focused Ion Beam) is used for sample preparation, machining a trench parallel to the indentation surface. In this way, the crack growth can be better controlled and the problem may be modeled in two dimensions.The technique has been used to study crack propagation in patterned structures as a function of thin film composition and processing. The results obtained, in terms of crack length along each interface studied, correlate well with the fracture energy measured by four-point bending (4 PB) in blanket films of the same materials. Finite element modeling of the stress fields in the vicinity of the crack tip has been carried out to understand the crack paths observed.

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On the Study of Piezoresistive Stress Sensors for Microelectronic Packaging

Journal of Electronic Packaging ◽

10.1115/1.1414134 ◽

2000 ◽

Vol 124 (1) ◽

pp. 22-26 ◽

Cited By ~ 19

Author(s):

Ben-Je Lwo ◽

Ching-Hsing Kao ◽

Tung-Sheng Chen ◽

Yao-Shing Chen

Keyword(s):

Input Power ◽

Microelectronic Packaging ◽

Piezoresistive Sensors ◽

Four Point Bending ◽

Stress Sensors ◽

Linear Relationships ◽

Study Test ◽

As Stress ◽

Test Chips ◽

P Type

Stress measurements in microelectronic packaging through piezoresistive sensors take the advantage of both in-situ and nondestructive. In this study, test chips with both p-type and n-type piezoresistive stress sensors, as well as a heat source, were first designed, then manufactured by a commercialized foundry so that the uniformity of the test chips was expected. Both temperature and stress calibrations were next performed through a special designed MQFP (Metal Quad Flat Package) and four-point bending (4PB) structure, respectively. Measurements of stresses which are produced due to both manufacturing process and thermal effects on the test chips were finally executed, and approximately linear relationships were observed between stress and temperature as well as stress and input power. It is concluded that n-type piezoresistive stress sensors are able to extract stress in microelectronic packaging with good accuracy.

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Characterization of RF Sputtered ZnO Piezoelectric Films Using Transmission Electron Microscope

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100114050 ◽

1975 ◽

Vol 33 ◽

pp. 86-87

Author(s):

Kemining W. Yeh ◽

Richard S. Muller ◽

Wei-Kuo Wu ◽

Jack Washburn

Keyword(s):

Integrated Circuit ◽

Acoustic Waves ◽

New Technology ◽

Surface Acoustic Waves ◽

Electromechanical Properties ◽

Leading Role ◽

Saw Devices ◽

Transmission Electron ◽

High Degree

Considerable and continuing interest has been shown in the thin film transducer fabrication for surface acoustic waves (SAW) in the past few years. Due to the high degree of miniaturization, compatibility with silicon integrated circuit technology, simplicity and ease of design, this new technology has played an important role in the design of new devices for communications and signal processing. Among the commonly used piezoelectric thin films, ZnO generally yields superior electromechanical properties and is expected to play a leading role in the development of SAW devices.

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Failure Analysis of CDM-ESD Damage in a GaAs RFIC

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0215 ◽

2000 ◽

Author(s):

Amy Poe ◽

Steve Brockett ◽

Tony Rubalcava

Keyword(s):

Radio Frequency ◽

Failure Analysis ◽

Integrated Circuit ◽

Production Test ◽

Analysis Techniques ◽

Device Model ◽

Charged Device ◽

Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

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Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components

ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2008p0121 ◽

2008 ◽

Author(s):

Nicholas Randall ◽

Rahul Premachandran Nair

Keyword(s):

Mechanical Properties ◽

Quality Control ◽

Integrated Circuits ◽

Integrated Circuit ◽

Manufacturing Process ◽

Solder Bumps ◽

Initial Work ◽

Circuit Components ◽

Materials Used

Abstract With the growing complexity of integrated circuits (IC) comes the issue of quality control during the manufacturing process. In order to avoid late realization of design flaws which could be very expensive, the characterization of the mechanical properties of the IC components needs to be carried out in a more efficient and standardized manner. The effects of changes in the manufacturing process and materials used on the functioning and reliability of the final device also need to be addressed. Initial work on accurately determining several key mechanical properties of bonding pads, solder bumps and coatings using a combination of different methods and equipment has been summarized.

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Estimating time to onset of swine influenza symptoms after initial novel A(H1N1v) viral infection

Epidemiology and Infection ◽

10.1017/s0950268810002566 ◽

2010 ◽

Vol 139 (9) ◽

pp. 1418-1424 ◽

Cited By ~ 8

Author(s):

B. D. M. TOM ◽

A. J. VAN HOEK ◽

R. PEBODY ◽

J. McMENAMIN ◽

C. ROBERTSON ◽

...

Keyword(s):

Incubation Time ◽

Time Distribution ◽

Age Groups ◽

Swine Influenza ◽

Interval Censoring ◽

Limited Data ◽

History Of ◽

Influenza Case ◽

Time To Onset

SUMMARYCharacterization of the incubation time from infection to onset is important for understanding the natural history of infectious diseases. Attempts to estimate the incubation time distribution for novel A(H1N1v) have been, up to now, based on limited data or peculiar samples. We characterized this distribution for a generic group of symptomatic cases using laboratory-confirmed swine influenza case-information. Estimates of the incubation distribution for the pandemic influenza were derived through parametric time-to-event analyses of data on onset of symptoms and exposure dates, accounting for interval censoring. We estimated a mean of about 1·6–1·7 days with a standard deviation of 2 days for the incubation time distribution in those who became symptomatic after infection with the A(H1N1v) virus strain. Separate analyses for the <15 years and ⩾15 years age groups showed a significant (P<0·02) difference with a longer mean incubation time in the older age group.

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