Effect of Underfill Thermomechanical Properties on Thermal Cycling Fatigue Reliability of Flip-Chip Ball Grid Array

2004 ◽  
Vol 126 (4) ◽  
pp. 560-564 ◽  
Author(s):  
Tong Hong Wang ◽  
Yi-Shao Lai ◽  
Jenq-Dah Wu
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Ball Grid Array ◽  
Thermomechanical Properties ◽  
Creep Model ◽  
Fatigue Reliability ◽  
Element Analysis ◽  
Dimensional Finite Element ◽  
Real Behavior ◽  
Thermal Cycling Fatigue

Plane two-dimensional finite element analysis was applied to study the effect of underfill thermomechanical properties on the potential of thermal fatigue failure for flip-chip ball grid array. Two-stage as well as constant thermomechanical properties of underfills were manipulated to represent extremes of practical underfills. The steady-state creep model was incorporated for the eutectic solder bump to represent its real behavior. It was found from the parametric studies that the underfill with high Young’s modulus, low coefficient of thermal expansion, and high glass transition temperature leads to the longest service life.

Thermomechanical Design for Fine Pitch 3D-IC Packages

2012 ◽  
Vol 2012 (1) ◽  
pp. 001001-001009 ◽  
Author(s):  
Akihiro Horibe ◽  
Sayuri Kohara ◽  
Kuniaki Sueoka ◽  
Keiji Matsumoto ◽  
Yasumitsu Orii ◽  
...  
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
High Stress ◽  
High Viscosity ◽  
Thermomechanical Properties ◽  
Design Parameters ◽  
Element Analysis ◽  
Package Design ◽  
Fine Pitch ◽  
Silicon Vias

Low stress package design is one of the greatest challenges for the realization of reliable 3D integrated devices, since they are composed of elements susceptible to failures under high stress such as thin dies, metal through silicon vias (TSVs), and fine pitch interconnections. In variety of package components, an organic interposer is a key to obtain low cost modules with high density I/Os. However, the large mismatch in coefficient of thermal expansion (CTE) between silicon dies and organic laminates causes high stress in an organic package. The major parametric components in 3D devices are dies with /without Cu-TSVs, laminates, bumps, and underfill layers. Especially, the die thicknesses and underfill properties are ones of the parameters that give us some range to control as package design parameters. In general, the underfill material with a high modulus and a low CTE is effective in reducing the stress in solder interconnections between the Si die and the laminate. However, the filler content of underfill materials with such mechanical properties generally results in high viscosity. The use of high viscous materials in between silicon dies in 3D modules can degrade process ability in 3D integration. In this study, we show that the interchip underfills in 3D modules have a wider mechanical property window than in 2D modules even with fine pitch interconnections consisting mostly of intermetallic compounds (IMCs). Also the finite element analysis results show that the optimization of the structural or thermomechanical properties of organic laminates and interchip underfill contributes to reduction of stressing thinned silicon dies which may have some risks to the device performance.

Experiment and Numerical Analysis of the Residual Stresses in Underfill Resins for Flip Chip Package Applications

2005 ◽  
Vol 127 (1) ◽  
pp. 47-51 ◽  
Author(s):  
Man-Lung Sham ◽  
Jang-Kyo Kim
Keyword(s):  
Numerical Analysis ◽  
Residual Stresses ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Flexural Modulus ◽  
Curing Temperature ◽  
Electronic Packages ◽  
Element Analysis ◽  
Plastic Package

Polymeric encapsulant is widely used to protect the integrated circuit chips and thus to enhance the reliability of electronic packages. Residual stresses are introduced in the plastic package when the polymer is cooled from the curing temperature to ambient, from which many reliability issues arise, including warpage of the package, premature interfacial failure, and degraded interconnections. Bimaterial strip bending experiment has been employed successfully to monitor the evolution of the residual stresses in underfrill resins for flip chip applications. A numerical analysis is developed to predict the residual stresses, which agree well with the experimental measurements. The changes of material properties, such as flexural modulus and coefficient of thermal expansion, of the resins with temperature are taken into account in the finite element analysis.

Stacking Yield Prediction of Package-on-Package Assembly Using Uncertainty Propagation Analysis—Part II: Implementation of Stochastic Model

2019 ◽  
Vol 142 (1) ◽  
Author(s):  
Hsiu-Ping Wei ◽  
Yu-Hsiang Yang ◽  
Bongtae Han
Keyword(s):  
Stochastic Model ◽  
Flip Chip ◽  
Yield Loss ◽  
Uncertainty Propagation ◽  
Ball Grid Array ◽  
Surface Evolver ◽  
Element Analysis ◽  
Loss Prediction ◽  
Eigenvector Dimension Reduction ◽  
Input Variables

The stochastic model for yield loss prediction proposed in Part I is implemented for a package-on-package (PoP) assembly. The assembly consists of a stacked die thin flat ball grid array (TFBGA) as the top package and a flip chip ball grid array (fcBGA) as the bottom package. The top and bottom packages are connected through 216 solder joints of 0.5 mm pitch in two peripheral rows. The warpage values of the top and bottom package are calculated by finite element analysis (FEA), and the corresponding probability of density functions (PDFs) are obtained by the eigenvector dimension reduction (EDR) method. The solder ball heights of the top and bottom package and the corner pad joint heights are determined by surface evolver, and their PDFs are determined by the EDR method, too. Only 137 modeling runs are conducted to obtain all 549 PDFs in spite of the large number of input variables considered in the study (27 input variables). Finally, the noncontact open-induced staking yield loss of the PoP assembly is predicted from the PDFs.

Finite element analysis of thermal distributions of solder ball in flip chip ball grid array using ABAQUS

2013 ◽  
Vol 30 (1) ◽  
pp. 14-18 ◽  
Author(s):  
Yap Boon Kar ◽  
Noor Azrina Talik ◽  
Zaliman Sauli ◽  
Jean Siow Fei ◽  
Vithyacharan Retnasamy
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Solder Ball ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Element Analysis

An Optimization of Two-Steps Curing Profile to Eliminate Voids Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging

2010 ◽  
Vol 97-101 ◽  
pp. 23-27 ◽  
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Ball Grid Array ◽  
Statistic Analysis ◽  
Curing Process ◽  
Ceramic Ball ◽  
Die Attach ◽  
Ball Grid Array Package ◽  
Flip Chip Packaging ◽  
The Impact

Underfilling is the preferred process to reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. Voids formation in underfill is considered as failure in flip chip manufacturing process. Voids formation possibly caused by several factors such as poor soldering and flux residue during die attach process, voids entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the optimization of two steps curing profile in order to reduce voids formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids after curing process. Statistic analysis was conducted to analyze the suitable curing profile in order to minimize or eliminate the voids formation. It was shown that the two steps curing profile provided solution for void elimination.

Warpage Analysis of Wafers With Film Coating

2001 ◽  
Author(s):  
Hai Ding ◽  
I. Charles Ume ◽  
Cheng Zhang
Keyword(s):  
Young’S Modulus ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Young's Modulus ◽  
Film Coating ◽  
Wafer Level ◽  
Element Analysis ◽  
Low Temperature Storage ◽  
Shadow Moire ◽  
Shadow Moiré

Abstract Wafer-level packaging (WLP) is one of the trends of electronic packaging in the 21st century. Since 1994, many companies have released WLP licenses. One of the common concerns among these various approaches is wafer warpage. Warpage of wafer tends to introduces crack or delamination during dicing and low temperature storage process. After wafer dicing, warpage could reduce the quality of each package in the long run. Many documented works indicated that in the design and implementation of WLP, some key parameters have to be carefully considered and closely controlled to ensure higher packaging quality with the minimum warpage. For the case of wafer-level flip chip, the key parameters are Young’s modulus, thickness, and coefficient of thermal expansion (CTE) of underfill. In this research, an experimental design and statistical methods have been used to identify the model structure and parameters that are critical to the warpage of wafers. Regression models were identified based on the data obtained from finite element analysis (FEA) that is verified by shadow Moiré experiments. According to the models, the CTE, the coupling of Young’s modulus and CTE, and the coupling of thickness and CTE of underfill primarily determine wafer warpage. Further FEA and shadow Moiré experiments indicate that the models are capable of predicting of wafer warpage in the process of WLP.

Reliability Analysis of Flip Chip Designs Via Computer Simulation

2000 ◽  
Vol 122 (3) ◽  
pp. 214-219 ◽  
Author(s):  
Hua Lu ◽  
C. Bailey ◽  
M. Cross
Keyword(s):  
Material Properties ◽  
Flip Chip ◽  
Thermal Loading ◽  
Coefficient Of Thermal Expansion ◽  
Empirical Relationship ◽  
Life Time ◽  
Fatigue Reliability ◽  
Chip Design ◽  
Flip Chips ◽  
Out Of Plane

A flip chip component is a silicon chip mounted to a substrate with the active area facing the substrate. This paper presents the results of an investigation into the relationship between a number of important material properties and geometric parameters on the thermal-mechanical fatigue reliability of a standard flip chip design and a flip chip design with the use of microvias. Computer modeling has been used to analyze the mechanical conditions of flip chips under cyclic thermal loading where the Coffin-Manson empirical relationship has been used to predict the life time of the solder interconnects. The material properties and geometry parameters that have been investigated are the Young’s modulus, the coefficient of thermal expansion (CTE) of the underfill, the out-of-plane CTE CTEz of the substrate, the thickness of the substrate, and the standoff height. When these parameters vary, the predicted life-times are calculated and some of the features of the results are explained. By comparing the predicted lifetimes of the two designs and the strain conditions under thermal loading, the local CTE mismatch has been found to be one of most important factors in defining the reliability of flip chips with microvias. [S1043-7398(00)01203-2]

Comparative Studies on Solder Joint Reliability of Plastic and Ceramic Ball Grid Array Packages of the Same Form Factor Under Power and Accelerated Thermal Cycling

2008 ◽  
Vol 130 (4) ◽  
Author(s):  
S. B. Park ◽  
Rahul Joshi ◽  
Izhar Ahmed ◽  
Soonwan Chung
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Loading ◽  
Ball Grid Array ◽  
Element Analysis ◽  
Severe Condition ◽  
Experimental Stress Analysis ◽  
Computational Fluid Dynamics Analysis ◽  
Accelerated Thermal Cycling ◽  
Ball Grid Array Packages

Experimental and numerical techniques are employed to assess the thermomechanical behavior of ceramic and organic flip chip packages under power cycling (PC) and accelerated thermal cycling (ATC). In PC, nonuniform temperature distribution and different coefficients of thermal expansion of each component make the package deform differently compared to the case of ATC. Traditionally, reliability assessment is conducted by ATC because ATC is believed to have a more severe thermal loading condition compared to PC, which is similar to the actual field condition. In this work, the comparative study of PC and ATC was conducted for the reliability of board level interconnects. The comparison was made using both ceramic and organic flip chip ball grid array packages. Moiré interferometry was adopted for the experimental stress analysis. In PC simulation, computational fluid dynamics analysis and finite element analysis are performed. The assembly deformations in numerical simulation are compared with those obtained by Moiré images. It is confirmed that for a certain organic package PC can be a more severe condition that causes solder interconnects to fail earlier than in ATC while the ceramic package fails earlier in ATC always.

Warpage Analysis of Underfilled Wafers

2004 ◽  
Vol 126 (2) ◽  
pp. 265-270 ◽  
Author(s):  
Hai Ding ◽  
I. Charles Ume ◽  
Cheng Zhang
Keyword(s):  
Young’S Modulus ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Young's Modulus ◽  
Wafer Level ◽  
Element Analysis ◽  
Low Temperature Storage ◽  
Shadow Moire ◽  
Shadow Moiré

Wafer-level packaging (WLP) is one of the future trends in electronic packaging. Since 1994, many companies have released various WLP licenses. One of the common concerns of WLP is wafer warpage. Warpage of wafers tends to introduce cracking or delamination during dicing and low temperature storage processes. After wafer dicing, warpage could affect the quality of the dies and shorten the life of each packaged product. Many documented works indicated that in the design and implementation of multilayer structured electronic packaging products, some key parameters must be carefully considered and closely controlled to ensure the best packaging quality with the minimum warpage. During the wafer-level flip chip assembly process, the application of underfill on the whole wafer is a critical step. In this step, the key underfill parameters that affect wafer warpage are Young’s modulus, thickness, and coefficient of thermal expansion (CTE). In this paper, an experimental design and statistical methods were used to identify the model structure and parameters that are critical to the warpage of wafers. Bilinear regression models were identified based on the data obtained from finite element analysis (FEA) that was verified by shadow moire´ experiments. In FEA, the underfilled wafer structure is simplified to consisting of two layers of linear elastic materials. According to the models, the CTE, the coupling of Young’s modulus and CTE, and the coupling of thickness and CTE primarily determine wafer warpage. Further FEA and shadow moire´ experiments indicate that the models are capable of predicting wafer warpage in the WLP processes.

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