Thermoelectric Micro-Cooler for Hot-Spot Thermal Management

Author(s):  
Peng Wang ◽  
Avram Bar-Cohen ◽  
Bao Yang ◽  
Gary L. Solbrekken ◽  
Yan Zhang ◽  
...  

Driven by shrinking feature sizes, microprocessor “hot-spots” — with their associated high heat flux and sharp temperature gradients — have emerged as the primary “driver” for on-chip thermal management of today’s IC technology. Solid state thermoelectric micro-coolers offer great promise for reducing the severity of on-chip “hot-spots”, but the theoretical cooling potential of these devices, fabricated on the back of the silicon die in an IC package, has yet to be determined. The results of a three-dimensional electro-thermal finite-element modeling study of such a micro-cooler are presented. Attention is focused on the hot-spot temperature reductions associated with variations in micro-cooler geometry, chip thickness, and chip doping concentration, along with the parasitic Joule heating effects from the electrical contact resistance and current flow through the silicon. The modeling results help to define the optimum solid-state cooling configuration and reveal that, for the conditions examined, nearly 80% of the hot-spot temperature rise of 2.5°C can be removed from a 70μm × 70μm, 680W/cm2 hot-spot on a 50μm thick silicon die with a single micro-cooler.

Author(s):  
Horacio Nochetto ◽  
Peng Wang ◽  
Avram Bar-Cohen

Driven by shrinking feature sizes, microprocessor hot spots have emerged as the primary driver for on-chip cooling of today’s IC technologies. Current thermal management technologies offer few choices for such on-chip hot spot remediation. A solid state germanium self-cooling layer, fabricated on top of the silicon chip, is proposed and demonstrated to have great promise for reducing the severity of on-chip hot spots. 3D thermo-electrical coupled simulations are used to investigate the effectiveness of a bi-layer device containing a germanium self-cooling layer above an electrically insulated silicon layer. The parametric variables of applied current, cooler size, silicon percentage, and total die thickness are sequentially optimized for the lowest hot spot temperature compared to a non-self-cooled silicon chip. Results suggest that the localized self-cooling of the germanium layer coupled with the higher thermal conductivity of the silicon chip can significantly reduce the temperature rise resulting from a micro-scaled hot spot.


Author(s):  
Peng Wang ◽  
Avram Bar-Cohen

Growing interest in germanium solid-state devices is raising concern over the effects of on-chip, micro-scaled, high flux hot spot on the reliability and performance of germanium chips. Current thermal management technology offers few choices for such on-chip hot spot remediation. However, the good thermo-electric properties of single crystal germanium support the development of a novel thermal management approach, relying on thermoelectric self-cooling by an electric current flowing in a thin planar layer on the back of the germanium chip. Use of metal-on-germanium fabrication techniques can yield a very low thermal contact resistance at the micro cooler/chip interface and the current flow can transfer the energy absorbed from a hot spot to the edge of the chip, thus substantially reducing the detrimental effect of thermoelectric heating on the temperature of the active circuitry. In this paper three-dimensional thermo-electric simulations are used to investigate the self-cooling of hot spots on a germanium chip for a wide range of input current, doping concentration, hot spot heat flux, micro cooler size, and germanium chip thickness. Results suggest that localized thermoelectric self-cooling on the germanium chip can significantly reduce the temperature rise resulting from micro-scaled high-flux hot spots.


2012 ◽  
Vol 134 (5) ◽  
Author(s):  
Avram Bar-Cohen ◽  
Peng Wang

The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip hot spots. The application of on-chip high flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric micro-coolers and two-phase microgap coolers. The advantages and disadvantages of these on-chip cooling solutions for high heat flux hot spots are evaluated and compared.


2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.


Author(s):  
Peng Wang ◽  
Avram Bar-Cohen

Thermal management of on-chip hot spots has become an increasing challenge in recent years because such localized high flux hot spots can not be effectively removed by conventional cooling techniques. The authors have recently explored the novel use of the silicon chip itself as a solid state thermoelectric micrcooler (μTEC) for hot spot thermal management. This paper describes the development and application of a thermo-electric design tool based on closed-form equations for the primary variables. This tool can be used to effectively reduce the complexity and required time for the design and optimization of the silicon microcooler geometry and material properties for on-chip hot spot remediation.


Author(s):  
Avram Bar-Cohen ◽  
Peng Wang

The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip “hot spots”. The application of on-chip high heat flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric microcoolers — using mini-contcat enhancement and in-plane thermoelectric currents, orthotropic TIM’s/heat spreaders, and phase-change microgap coolers.


Author(s):  
Viatcheslav Litvinovitch ◽  
Avram Bar-Cohen

Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors and other electronic components, have lead to the emergence of severe on-chip “hot spots,” with heat fluxes approaching — and at times exceeding — 1 kW/cm2. The cost-effective thermal management of such chips requires the introduction and refinement of novel cooling techniques. Mini-contact enhanced, miniaturized thermoelectric coolers (TECs) have been shown to be a viable approach for the remediation of on-chip hot spots, but their performance is constrained by the thermal resistance introduced by the attachment of this thermal management device. This paper uses a detailed finite-element package-level model to examine the parasitic effects of the thermal contact resistance (at the interfaces of the mini-contact and TEC) on the cooling efficacy of this thermal solution. Particular attention is devoted to the deleterious effect of contact resistance on the thermoelectric leg height and the mini-contact size required to achieve the greatest hot spot temperature reduction on the chip. Data from experiments with TECs (with a leg height of 130 μm) combined with several sizes of mini-contact pads, are used to validate the modeling approach and the overall conclusions.


Author(s):  
Gary L. Solbrekken

Localized areas of high heat flux on microprocessors are currently being identified as a dominant challenge for the thermal management community. Heat flux values up to 1 kW/cm2 prevailing over a fraction of the overall CPU surface area create local hot spots that need to be cooled. However, thermal solutions designed for the maximum heat flux overcool the rest of the CPU, wasting resources and creating large on-die temperature gradients. Wasting resources obviously has a negative economic and thermodynamic impact. However, it has been argued that large on-die temperature gradients reduce chip reliability and increase the difficulty in laying out the electric circuits. The current study proposes a strategy to reduce local hot spots by enhancing heat spreading through the use of the Peltier effect. The Peltier effect is most commonly associated with the operation of thermoelectric modules. In thermoelectric modules, heat is transported across the module by electrons. Ideally, the material used for the thermoelectric module would have a very low thermal conductivity to reduce the amount of back heat conduction through the thermoelectric elements, and the electric resistivity would be very low to minimize the Joule heating. Using today’s best commercially available thermoelectric materials, the thermal conductivity, electric resistivity, and Seebeck coefficient are such that the COP for the thermoelectric module is on the order of 1. This implies that in order to cool a processor dissipating 100W, an additional 100W of electric power must be supplied to the thermoelectric module. A total of 200W must then be rejected by the heat sink and any building HVAC system. A more pragmatic approach is to use the Peltier effect to not cool the entire CPU, but rather only the high heat flux region. This is accomplished by placing the thermoelectric elements laterally on the backside of the CPU. The cooling junction is placed in the proximity of the high flux region, while the heating junction is placed in contact with the CPU in low heat flux area that can tolerate the additional heat, effectively creating an active heat spreader. The Peltier enhanced heat spreading proposed here is shown to provide a reduction in the temperature of a localized hot spot relative to passive heat spreading. The amount of reduction in temperature depends on the thickness of the material as well as the thermal conductivity, but values up to 50% are illustrated.


This paper describes an experimental study of the initiation of solid explosives, and in particular the effect of artificially introducing transient hot spots of known maximum temperature. This was done by adding small foreign particles (or grit) of known melting-point. The minimum transient hot-spot temperature for the initiation of a number of secondary and primary explosives has been determined in this way. It is shown that the melting-point of the grit is the determining factor , and all the grits which sensitize these explosives to initiation either by friction or impact have melting-points above a threshold value which lies between 400 and 550 ° C. Grit particles of lower melting-point do not sensitize the explosives. The same explosives initiated by the adiabatic compression of air required, for initiation, minimum transient temperatures of the same order as the threshold melting-point values. The results provide strong evidence that the initiation of solids as well as of liquids by friction and impact is thermal in origin and is due to the formation of localized hot spots. There is evidence that in the case of the majority of secondary explosives which melt at comparatively low temperatures, intergranular friction is not able to cause explosion and the hot spots must be formed in some other way. With the primary explosives which explode at temperatures below their melting-points, hot spots formed by intergranular friction can be important.


Author(s):  
Zhengang Zhao ◽  
Zhangnan Jiang ◽  
Yang Li ◽  
Chuan Li ◽  
Dacheng Zhang

The temperature of the hot-spots on windings is a crucial factor that can limit the overload capacity of the transformer. Few studies consider the impact of the load on the hot-spot when studying the hot-spot temperature and its location. In this paper, a thermal circuit model based on the thermoelectric analogy method is built to simulate the transformer winding and transformer oil temperature distribution. The hot-spot temperature and its location under different loads are qualitatively analyzed, and the hot-spot location is analyzed and compared to the experimental results. The results show that the hot-spot position on the winding under the rated power appears at 85.88% of the winding height, and the hot-spot position of the winding moves down by 5% in turn at 1.3, 1.48, and 1.73 times the rated power respectively.


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