Silicon Hot Spot Remediation With a Germanium Self Cooling Layer

2011 ◽  
Author(s):  
Horacio Nochetto ◽  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Hot Spots ◽  
Hot Spot ◽  
Silicon Layer ◽  
Great Promise ◽  
Applied Current ◽  
Chip Cooling ◽  
Primary Driver ◽  
Germanium Layer ◽  
On Chip ◽  
Spot Temperature

Driven by shrinking feature sizes, microprocessor hot spots have emerged as the primary driver for on-chip cooling of today’s IC technologies. Current thermal management technologies offer few choices for such on-chip hot spot remediation. A solid state germanium self-cooling layer, fabricated on top of the silicon chip, is proposed and demonstrated to have great promise for reducing the severity of on-chip hot spots. 3D thermo-electrical coupled simulations are used to investigate the effectiveness of a bi-layer device containing a germanium self-cooling layer above an electrically insulated silicon layer. The parametric variables of applied current, cooler size, silicon percentage, and total die thickness are sequentially optimized for the lowest hot spot temperature compared to a non-self-cooled silicon chip. Results suggest that the localized self-cooling of the germanium layer coupled with the higher thermal conductivity of the silicon chip can significantly reduce the temperature rise resulting from a micro-scaled hot spot.

Thermoelectric Micro-Cooler for Hot-Spot Thermal Management

2005 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen ◽  
Bao Yang ◽  
Gary L. Solbrekken ◽  
Yan Zhang ◽  
...  
Keyword(s):  
Solid State ◽  
Thermal Management ◽  
Hot Spots ◽  
Hot Spot ◽  
Electrical Contact ◽  
Chip Thickness ◽  
Great Promise ◽  
High Heat Flux ◽  
On Chip ◽  
Spot Temperature

Driven by shrinking feature sizes, microprocessor “hot-spots” — with their associated high heat flux and sharp temperature gradients — have emerged as the primary “driver” for on-chip thermal management of today’s IC technology. Solid state thermoelectric micro-coolers offer great promise for reducing the severity of on-chip “hot-spots”, but the theoretical cooling potential of these devices, fabricated on the back of the silicon die in an IC package, has yet to be determined. The results of a three-dimensional electro-thermal finite-element modeling study of such a micro-cooler are presented. Attention is focused on the hot-spot temperature reductions associated with variations in micro-cooler geometry, chip thickness, and chip doping concentration, along with the parasitic Joule heating effects from the electrical contact resistance and current flow through the silicon. The modeling results help to define the optimum solid-state cooling configuration and reveal that, for the conditions examined, nearly 80% of the hot-spot temperature rise of 2.5°C can be removed from a 70μm × 70μm, 680W/cm2 hot-spot on a 50μm thick silicon die with a single micro-cooler.

Investigation of On-Chip Hot Spot Cooling Using Microchannel Heat Sink

2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang
Keyword(s):  
Heat Flux ◽  
Heat Sink ◽  
Hot Spots ◽  
Hot Spot ◽  
High Heat ◽  
High Heat Flux ◽  
Microchannel Heat Sink ◽  
Three Dimensional Model ◽  
Spot Cooling ◽  
On Chip

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.

scholarly journals Initiation of solid explosives by impact and friction: the influence of grit

1949 ◽  
Vol 198 (1054) ◽  
pp. 337-349 ◽  
Keyword(s):  
Melting Point ◽  
Hot Spots ◽  
Hot Spot ◽  
Threshold Value ◽  
Maximum Temperature ◽  
Melting Points ◽  
Solid Explosives ◽  
Lower Melting Point ◽  
Determining Factor ◽  
Spot Temperature

This paper describes an experimental study of the initiation of solid explosives, and in particular the effect of artificially introducing transient hot spots of known maximum temperature. This was done by adding small foreign particles (or grit) of known melting-point. The minimum transient hot-spot temperature for the initiation of a number of secondary and primary explosives has been determined in this way. It is shown that the melting-point of the grit is the determining factor , and all the grits which sensitize these explosives to initiation either by friction or impact have melting-points above a threshold value which lies between 400 and 550 ° C. Grit particles of lower melting-point do not sensitize the explosives. The same explosives initiated by the adiabatic compression of air required, for initiation, minimum transient temperatures of the same order as the threshold melting-point values. The results provide strong evidence that the initiation of solids as well as of liquids by friction and impact is thermal in origin and is due to the formation of localized hot spots. There is evidence that in the case of the majority of secondary explosives which melt at comparatively low temperatures, intergranular friction is not able to cause explosion and the hot spots must be formed in some other way. With the primary explosives which explode at temperatures below their melting-points, hot spots formed by intergranular friction can be important.

scholarly journals Effect of Loads on Temperature Distribution Characteristics of Oil-Immersed Transformer Winding

2021 ◽  
Author(s):  
Zhengang Zhao ◽  
Zhangnan Jiang ◽  
Yang Li ◽  
Chuan Li ◽  
Dacheng Zhang
Keyword(s):  
Temperature Distribution ◽  
Hot Spots ◽  
Hot Spot ◽  
Transformer Oil ◽  
Distribution Characteristics ◽  
Thermal Circuit ◽  
Transformer Winding ◽  
Overload Capacity ◽  
The Impact ◽  
Spot Temperature

The temperature of the hot-spots on windings is a crucial factor that can limit the overload capacity of the transformer. Few studies consider the impact of the load on the hot-spot when studying the hot-spot temperature and its location. In this paper, a thermal circuit model based on the thermoelectric analogy method is built to simulate the transformer winding and transformer oil temperature distribution. The hot-spot temperature and its location under different loads are qualitatively analyzed, and the hot-spot location is analyzed and compared to the experimental results. The results show that the hot-spot position on the winding under the rated power appears at 85.88% of the winding height, and the hot-spot position of the winding moves down by 5% in turn at 1.3, 1.48, and 1.73 times the rated power respectively.

Simplified Thermal Model of Silicon Thermoelectric Microcooler for On-Chip Hot Spot Remediation

2007 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Thermal Management ◽  
Material Properties ◽  
Hot Spots ◽  
Hot Spot ◽  
Design Tool ◽  
The Novel ◽  
Thermo Electric ◽  
Design And Optimization ◽  
Conventional Cooling ◽  
On Chip

Thermal management of on-chip hot spots has become an increasing challenge in recent years because such localized high flux hot spots can not be effectively removed by conventional cooling techniques. The authors have recently explored the novel use of the silicon chip itself as a solid state thermoelectric micrcooler (μTEC) for hot spot thermal management. This paper describes the development and application of a thermo-electric design tool based on closed-form equations for the primary variables. This tool can be used to effectively reduce the complexity and required time for the design and optimization of the silicon microcooler geometry and material properties for on-chip hot spot remediation.

Array of Thermoelectric Coolers for On-Chip Thermal Management

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Owen Sullivan ◽  
Man Prakash Gupta ◽  
Saibal Mukhopadhyay ◽  
Satish Kumar
Keyword(s):  
Steady State ◽  
Current Pulse ◽  
Hot Spots ◽  
Hot Spot ◽  
High Amplitude ◽  
Peak Temperature ◽  
Thermoelectric Coolers ◽  
Electronic Package ◽  
Current Pulses ◽  
On Chip

Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time. An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip. This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way. Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation. Transient operation of TECs is capable of driving cold-side temperatures below steady-state values. Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak. Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots.

Thermal Management of On-Chip Hot Spot

2009 ◽  
Author(s):  
Avram Bar-Cohen ◽  
Peng Wang
Keyword(s):  
Heat Flux ◽  
Thermal Management ◽  
Hot Spot ◽  
High Heat ◽  
High Heat Flux ◽  
Switching Speed ◽  
Primary Driver ◽  
Management Approaches ◽  
On Chip ◽  
Physical Phenomena

The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip “hot spots”. The application of on-chip high heat flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric microcoolers — using mini-contcat enhancement and in-plane thermoelectric currents, orthotropic TIM’s/heat spreaders, and phase-change microgap coolers.

Effect of Thermal Contact Resistance on Optimum Mini-Contact TEC Cooling of On-Chip Hot Spots

2009 ◽  
Author(s):  
Viatcheslav Litvinovitch ◽  
Avram Bar-Cohen
Keyword(s):  
Contact Resistance ◽  
Thermal Management ◽  
Hot Spots ◽  
High Performance ◽  
Thermal Contact Resistance ◽  
Hot Spot ◽  
Thermal Contact ◽  
Heat Fluxes ◽  
Thermoelectric Coolers ◽  
On Chip

Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors and other electronic components, have lead to the emergence of severe on-chip “hot spots,” with heat fluxes approaching — and at times exceeding — 1 kW/cm2. The cost-effective thermal management of such chips requires the introduction and refinement of novel cooling techniques. Mini-contact enhanced, miniaturized thermoelectric coolers (TECs) have been shown to be a viable approach for the remediation of on-chip hot spots, but their performance is constrained by the thermal resistance introduced by the attachment of this thermal management device. This paper uses a detailed finite-element package-level model to examine the parasitic effects of the thermal contact resistance (at the interfaces of the mini-contact and TEC) on the cooling efficacy of this thermal solution. Particular attention is devoted to the deleterious effect of contact resistance on the thermoelectric leg height and the mini-contact size required to achieve the greatest hot spot temperature reduction on the chip. Data from experiments with TECs (with a leg height of 130 μm) combined with several sizes of mini-contact pads, are used to validate the modeling approach and the overall conclusions.

Study of the Hot Spots in Integrated Circuits Cooled by Microfluidic Heatsinks

2007 ◽  
Author(s):  
Alireza Motieifar ◽  
Cyrus Shafai ◽  
Hassan M. Soliman
Keyword(s):  
Fluid Flow ◽  
Integrated Circuits ◽  
Heat Sink ◽  
Hot Spots ◽  
Hot Spot ◽  
Solid Material ◽  
Heat Fluxes ◽  
Heat Sinks ◽  
Fem Method ◽  
Spot Temperature

The thermal input into high-power Integrated Circuits (IC) can have local peaks or hot spots with heat fluxes far exceeding 100 W/cm2. In this work, the temperature distribution on a microfluidic heatsink has been simulated using the FEM method. The effects of the fluid flow and thickness of the heatsink on the hot spot temperature have been studied. Simulations have been performed for a 1 cm × 1 cm heat sink loaded with 100 W/cm2 heating power, with a 1 mm hot spot of 1000 W/cm2 and a 3 mm hot spot of 500 W/cm2. Heat sinks fabricated from silicon, nickel, and copper are considered. These results show that the effect of increasing the thickness of the heatsink on the peak temperature of the hot spot depends on the solid material and the fluid flow. Simulations showed that the hot spot temperature rise can be about 40% higher if a nickel heat sink is used instead of a copper heat sink.

Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies

2013 ◽  
Vol 135 (2) ◽  
Author(s):  
Wataru Nakayama
Keyword(s):  
Hot Spots ◽  
High Performance ◽  
Thermal Environment ◽  
Hot Spot ◽  
Air Cooling ◽  
Multicore Processor ◽  
Temperature Contrast ◽  
On Chip ◽  
Heat Spreading ◽  
Level Analysis

The objective of this study is to understand the effects of various parameters involved in the chip design and cooling on the occurrence of hot spots on a multicore processor chip. The thermal environment for the die is determined by the cooling design which differs distinctly between different classes of electronic equipment. In the present study, like many other hot spot studies, the effective heat transfer coefficient represents the thermal environment for the die, but, its representative values are derived for different cooling schemes in order to examine in what classes of electronic equipment the hot spot concern grows. The cooling modes under study are high-performance air-cooling, high-performance liquid-cooling, conventional air-cooling, and oil-cooling in infrared radiation (IR) thermography setup. Temperature calculations were performed on a model which is designed to facilitate the study of several questions that have not been fully addressed in the existing literature. These questions are concerned with the granularity of power and temperature distributions, thermal interactions between circuits on the die, the roles of on-chip wiring layer and the buried dioxide in heat spreading, and the mechanism of producing temperature contrast across the die. The main results of calculations are the temperature of the target spot and the temperature contrast across the die. Temperature contrasts are predicted in a range 10–25 K, and the results indicate that a major part of the temperature contrast is formed at a granularity corresponding to the size of functional units on actual microprocessor chips. At a fine granularity level and under a scenario of high power concentration, the on-chip wiring layer and the buried oxide play some roles in heat spreading, but their impact on the temperature is generally small. However, the details of circuits need to be taken into account in future studies in order to investigate the possibility of nanometer-scale hot spots. Attention is also called to the need to understand the effect of temperature nonuniformity on the processor performance for which low temperature at inactive cells makes a major contribution. In contrast to the situation for the die under forced convection cooling, the die in passively cooled compact equipment is in distinctly different thermal environment. Strong thermal coupling between the die and the system structure necessitates the integration of package and system level analysis with the die-level analysis.

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