A Slim Sector Model for the Analysis of Fatigue Life of Fine Pitch Flip Chip Packages

2005 ◽  
Author(s):  
Bing Zhao ◽  
Andrew A. O. Tay
Keyword(s):  
Fatigue Life ◽  
Flip Chip ◽  
Computation Time ◽  
Critical Issue ◽  
Temperature Cycling ◽  
Element Analysis ◽  
Sector Model ◽  
Fine Pitch ◽  
Time Required ◽  
Diagonal Plane

In the near future, it is likely that the interconnection pitch of flip chips will fall below 100 microns. For a flip chip of 20mm × 20mm at this pitch, there will be 40,000 interconnections on the chip. Even after taking advantage of symmetry whereby only a one-eighth model need be analyzed, there will be 5,000 interconnections. If solder were used to form the interconnection, plasticity and creep effects would need to be taken into account. Despite the great advances in computer technology, the computer memory and computation time required for a full 3D finite element analysis (FEA) of such a fine-pitch IC package is prohibitive. This paper presents a slim sector model which could be used to overcome this problem. Essentially, a slim sector of the package adjacent to the diagonal is analyzed rather than a 1/8 model. The appropriate boundary condition to be applied to the slim sector model is a critical issue. With the large number of interconnections, it is reasonable to expect that the displacement of points close to the diagonal plane of the package will tend to be directed radially outwards from the neutral point at the centre of the package. The validity of this assumption was investigated by performing a full 3D FEA of the 1/8 model of two flip chip packages of dimensions 4mm square and 6mm square. A few slim sector models have been developed and their accuracy and computational efficiency studied. The fatigue life of the critical solder joint was determined by performing a temperature cycling simulation between −40C and 150C. The elastoplastic and creep properties of solder were taken into account. As the 1/8 model is the most accurate model, its results were taken as reference. It was found that the accuracy of the best slim sector model ranged between 12% and 27%. A comparison was also made between the slim sector model and the popular strip model. It was found that the slim sector model was much more accurate than the strip model which gives error of 61–248%.

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001870-001893
Author(s):  
Rajesh Katkar ◽  
Zhijun Zhao ◽  
Ron Zhang ◽  
Rey Co ◽  
Laura Mirkarimi
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Memory Bandwidth ◽  
Free Standing ◽  
Element Analysis ◽  
Fine Pitch ◽  
Solder Balls ◽  
High Bandwidth ◽  
Reliability Performance

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

scholarly journals Efficient Distortion Prediction of Additively Manufactured Parts Using Bayesian Model Transfer Between Material Systems

2020 ◽  
Vol 142 (5) ◽  
Author(s):  
Jack Francis ◽  
Arman Sabbaghi ◽  
M. Ravi Shankar ◽  
Morteza Ghasri-Khouzani ◽  
Linkan Bian
Keyword(s):  
Bayesian Model ◽  
Computation Time ◽  
Critical Issue ◽  
Material System ◽  
Element Analysis ◽  
Distortion Model ◽  
Material Systems ◽  
New Material ◽  
Model Transfer

Abstract Distortion in laser-based additive manufacturing (LBAM) is a critical issue that adversely affects the geometric integrity of additively manufactured parts and generally exhibits a complicated dependence on the underlying material. The differences in properties between distinct materials prevent the immediate application of a distortion model learned for one material to another, which introduces the challenge in LBAM of learning a distortion model for a new material system given past experiments. Current methods for investigating the distortion of different material systems typically involve finite element analysis or a large number of experiments in an empirical study. However, these methods do not learn from previous experiments and can incur significant costs in terms of computation, time, or resources. We propose a Bayesian model transfer methodology that is both physics-based and data-driven to leverage past experiments on previously studied material systems for more efficient distortion modeling of new systems. This method transfers distortion models across distinct materials based on the statistical effect equivalence framework by formulating the differences between two materials as a lurking variable. Our method reduces the experimentation and effort needed for specifying distortion models for new material systems. We validate our methodology in a case study of distortion model transfer from Ti–6Al–4V disks to 316L stainless steel disks. This case study is the first instance of model transfer between material systems and illustrates the ability of the Bayesian model transfer methodology to address the issue of comprehensive distortion modeling across varying material systems in LBAM.

Experimental and Numerical Evaluation of SnAgCu and SnPb Solders Using a MicroBGA Under Accelerated Temperature Cycling Conditions

2004 ◽  
Author(s):  
Bryan Rodgers ◽  
Jeff Punch ◽  
Claire Ryan ◽  
Finbarr Waldron ◽  
Liam Floyd
Keyword(s):  
Fatigue Life ◽  
Large Scale ◽  
Temperature Cycling ◽  
Lead Free ◽  
Model Parameters ◽  
Lead Free Solder ◽  
Element Analysis ◽  
Snagcu Solder ◽  
Numerical Predictions ◽  
Free Solder

A comparative evaluation of the leading lead-free solder candidate (95.5Sn3.8Ag0.7Cu) and traditional tin-lead solder (63Sn37Pb) under thermal cycling conditions was carried out. A test vehicle consisting of four daisy chained 10×10 array 0.8mm pitch plastic micro ball grid arrays (microBGA) mounted on an 8-layer FR4 printed wiring board was designed. The board finish was organic solder preservative (OSP) for the lead-free devices and hot air solder levelled (HASL) in the case of the eutectic devices. An event detector was used to monitor the continuity of each daisy chain during accelerated temperature cycling, where the test vehicles were cycled with a ramp rate of approximately 3°C per minute from −40°C to 125°C, with 10-minute dwells and a total cycle time of 2 hours 10 minutes. Results to date plotted using a Weibull distribution indicate that the SnAgCu solder is more reliable under these conditions. Experiments were also carried out on large-scale lead-free solder specimens to determine the parameters required for the Anand viscoplasticity model. The Anand model was then implemented in finite element analysis using ANSYS®, where the submodelling technique was employed to determine the viscoplastic work per thermal cycle for each solder joint along the package diagonal. Schubert’s fatigue life model was used to predict the number of cycles to failure of each joint, although it should be noted that the necessary model parameters for the may need to be calibrated. Results indicate that the joint under the die edge is likely to fail first and that the SnAgCu solder is more fatigue resistant. The numerical predictions underestimate the fatigue life in both cases.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

2011 ◽  
Vol 2011 (1) ◽  
pp. 000953-000960 ◽  
Author(s):  
Thomas Oppert ◽  
Rainer Dohle ◽  
Jörg Franke ◽  
Stefan Härter
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Solder Paste ◽  
Wafer Level ◽  
Solder Alloys ◽  
Flip Chips ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

Selection of Proper Fatigue Model for Flip Chip Package Reliability

2005 ◽  
Vol 502 ◽  
pp. 393-398 ◽  
Author(s):  
Young Eui Shin ◽  
Yeon Sung Kim ◽  
Hyoung-Il Kim ◽  
Jong Min Kim ◽  
Kyong Ho Chang ◽  
...  
Keyword(s):  
Fatigue Life ◽  
Flip Chip ◽  
Constitutive Models ◽  
Experimental Result ◽  
Element Analysis ◽  
Cross Sectional ◽  
Joint Reliability ◽  
Fatigue Model ◽  
Creep Fatigue ◽  
Number Of Cycles

There have been diverse fatigue models and approaches to properly estimate solder joint reliability. However, it is one of the most difficult problems to determine which solder constitutive models and fatigue models can be applied best. In this paper, both viscoplastic and elastic-plastic-creep solder constitutive models could be utilized to calculate accumulated inelastic response under 208 K to 423 K(-65 °C to 150 °C) thermal cycling condition. And two different fatigue models, Darveaux and creep-fatigue model were applied to find solder joints fatigue life for flip chip assembly. Moreover, each fatigue life was compared to experimental result for the validation of finite element analysis. The actual number of cycles to failure was obtained from cross sectional view of the package with SEM.

Flip Chip Packaging of Wafer Level Encapsulated RF MEMS Tunable Capacitors

2013 ◽  
Author(s):  
Shawn J. Cunningham ◽  
Yvonne Heng ◽  
Nabeel Idrisi ◽  
Brad Nelson ◽  
John McKillop
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Rf Mems ◽  
Temperature Cycling ◽  
Battery Life ◽  
Mems Devices ◽  
Wafer Level ◽  
Element Analysis ◽  
Tunable Capacitors ◽  
Flip Chip Packaging

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place. In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability. In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.

Effect of Corner Staking on the Fatigue Life of BGA Under Thermal Cycling

2017 ◽  
Author(s):  
Deng Yun Chen ◽  
Michael Osterman
Keyword(s):  
Fatigue Life ◽  
Thermal Cycling ◽  
Material Properties ◽  
Solder Joints ◽  
Material Selection ◽  
Temperature Cycling ◽  
Sac305 Solder ◽  
Element Analysis ◽  
Bga Packages ◽  
The Impact

Solder interconnects in electronic assemblies are susceptible to failures due to environmental high strain rate impact and cyclic stresses. To mitigate the failures, adhesive bonds can be added after the solder assembly process to provide additional mechanical support. For ball grid array (BGA) packages, the adhesive is normally applied to the corners of the package and referred to as corner staking. In addition to corner staking, underfill is also a strategy used to mitigate the stresses on the solder joints. While components with underfill has been widely studied, the study of the impact of corner staking on the reliability of packages remains limited. This paper presents a study of corner-staked BGA packages with tin-3.0 silver-0.5 copper (SAC305) solder subjected to temperature cycling. Experimental temperature cycling is conducted to examine impact of the selected corner staking material on the fatigue life of BGAs. Further, finite element analysis is conducted to understand the influence of material properties of staking material on the fatigue life of BGAs. The result of the study indicates that the presence of corner staking, with selected material properties, reduces the damage on the solder joints under thermal cycling, and thus increases its fatigue life by about 80%. This paper may serve as a guidance for staking material selection to improve the fatigue life of solder joints of BGAs under thermal cycling.

A Full-Scale 3D Finite Element Analysis for No-Underfill Flip Chip Package

2002 ◽  
Author(s):  
S. M. Hsu ◽  
J. C. Lin ◽  
K. N. Chiang
Keyword(s):  
Finite Element ◽  
Finite Element Model ◽  
Flip Chip ◽  
Computation Time ◽  
Element Model ◽  
Organic Substrate ◽  
Full Scale ◽  
Element Analysis ◽  
3D Finite Element ◽  
3D Finite Element Model

This research establishes a micro-macro 3D finite element model for no underfill flip chip BGA package. The no underfill package uses a ceramic-like (CTE close to silicon) material mounted on the backside of the flip chip substrate to constrain the thermal expansion of the organic substrate and enhance the reliability of the solder joint. This work attempts to design a constrained structure to enhance the reliability of the no underfill flip chip package. For the special design of constrained structure, a full-scale 3D finite element model is needed to investigate some mechanical behaviors that cannot be revealed by the 2D finite element model. However, to establish a full-scale 3D finite element model, the large computation time is an issue. The equivalent beam concept is adopted in this research to overcome this drawback of the finite element models. The results indicate that the equivalent beam concept is a feasible methodology for reducing the computation time of the 3D finite element model. Further, the new design structure could improve package reliability, increase manufacturing throughput and thermal performance, and maintain reworkability of the flip chip structure.

Application of Finite Element Method in Optimal Design of Flip-Chip Package

2011 ◽  
Vol 264-265 ◽  
pp. 1660-1665
Author(s):  
Yong Cheng Lin ◽  
Yu Chi Xia
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Solder Joint ◽  
Thermal Fatigue ◽  
Flip Chip ◽  
Solder Joints ◽  
Temperature Cycling ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder

More and more solder joints in circuit boards and electronic products are changing to lead free solder, placing an emphasis on lead free solder joint reliability. Solder joint fatigue failure is a serious reliability concern in area array technologies. In this study, the effects of substrate materials on the solder joint thermal fatigue life were investigated by finite element model. Accelerated temperature cycling loading was imposed to evaluate the reliability of solder joints. The thermal strain/stress in solder joints of flip chip assemblies with different substrates was compared, and the fatigue life of solder joints were evaluated by Darveaux’s crack initiation and growth model. The results show the mechanisms of substrate flexibility on improving solder joint thermal fatigue.

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