On the negative capacitance behavior in the forward bias of Au/n–4H–SiC (MS) and comparison between MS and Au/TiO2/n–4H–SiC (MIS) type diodes both in dark and under 200 W illumination intensity

2014 ◽  
Vol 29 (01) ◽  
pp. 1450237 ◽  
Author(s):  
H. G. Çetinkaya ◽  
D. E. Yıldız ◽  
Ş. Altındal
Keyword(s):  
Ideality Factor ◽  
Dielectric Material ◽  
Forward Bias ◽  
Reverse Current ◽  
Surface States ◽  
Negative Capacitance ◽  
Distribution Profile ◽  
Insulator Layer ◽  
Layer Width ◽  
Energy Density Distribution

In order to see the effect of interfacial layer on electrical characteristics both Au /n–4 H – SiC (MS) and Au/TiO 2/n–4 H – SiC (MIS) type Schottky barrier diodes (SBDs) were fabricated and their main electrical parameters were investigated by using the forward and reverse bias current-voltage (I–V), capacitance/conductance-voltage (C/G–V) measurements at room temperature. The ideality factor (n), series and shunt resistances (Rs, Rsh), barrier height (BH), depletion layer width (WD) and the concentration of donor atoms (ND) were obtained before and after illumination. The energy density distribution profile of surface states (Nss) was also obtained by taking into account voltage dependent effective BH (Φe) and ideality factor (nV). All of these experimental results confirmed that the use of a high dielectric material or insulator layer ( TiO 2) between metal and semiconductor leads to improvements in the diode performance in terms of Rs, Rsh, BH, Nss and rectifier rate (RR = IF/IR for sufficiently high forward and reverse current). Another important result is the negative capacitance (NC) behavior observed in the forward bias C–V plot for the Au /n–4 H – SiC (MS) diode, but it disappears in Au/TiO 2/n–4 H – SiC (MIS) diode and also the minimum value of C–V plot corresponds to maximum value of G/ω–V plot in the accumulation region. Such behavior of NC shows that the material displays an inductive behavior.

A comparative study on the electrical parameters of Au/n-Si Schottky diodes with and without interfacial (Ca1.9Pr0.1Co4Ox) layer

2016 ◽  
Vol 30 (16) ◽  
pp. 1650090 ◽  
Author(s):  
A. Kaya ◽  
H. G. Çetinkaya ◽  
Ş. Altındal ◽  
İ. Uslu
Keyword(s):  
Barrier Height ◽  
Room Temperature ◽  
Voltage Dependence ◽  
Schottky Diodes ◽  
Forward Bias ◽  
Surface States ◽  
Electrical Parameters ◽  
Distribution Profile ◽  
Text Data ◽  
Energy Density Distribution

In order to compare the main electrical parameters such as ideality factor [Formula: see text], barrier height (BH) [Formula: see text], series [Formula: see text] and shunt [Formula: see text] resistances and energy density distribution profile of surface states [Formula: see text], the [Formula: see text]-[Formula: see text] (MS) Schotthy diodes (SDs), with and without interfacial [Formula: see text] layer were obtained from the current–voltage [Formula: see text]–[Formula: see text] measurements at room temperature. The other few electrical parameters such as Fermi energy level [Formula: see text], BH [Formula: see text]), [Formula: see text] and voltage dependence of [Formula: see text] profile were also obtained from the capacitance–voltage [Formula: see text]–[Formula: see text] measurements. The voltage dependence of [Formula: see text] profile has two distinctive peaks in the depletion region for two diodes and they were attributed to a particular distribution of [Formula: see text] located at metal–semiconductor (MS) interface. All of these results have been investigated at room temperature and results have been compared with each other. Experimental results confirmed that interfacial [Formula: see text] layer enhanced diode performance in terms of rectifier rate [Formula: see text] at [Formula: see text], [Formula: see text] [Formula: see text]at [Formula: see text] and [Formula: see text] [Formula: see text] with values of 265, [Formula: see text] and [Formula: see text] for MS type Schottky barrier diode and [Formula: see text], [Formula: see text] and [Formula: see text] for metal–insulator–semiconductor (MIS) type SBD, respectively. It is clear that the rectifying ratio of MIS type SBD is about 9660 times greater than MS type SBD. The value of barrier height (BH) obtained from [Formula: see text]–[Formula: see text] data is higher than the forward bias [Formula: see text]–[Formula: see text] data and it was attributed to the nature of measurements. These results confirmed that the interfacial [Formula: see text] layer has considerably improved the performance of SD.

Pt/n-GaN metal-semiconductor and Pt/HfO2/n-GaN metal-insulator-semiconductor Schottky diodes

2014 ◽  
Vol 1736 ◽  
Author(s):  
Arjun Shetty ◽  
Basanta Roul ◽  
Shruti Mukundan ◽  
Greeshma Chandan ◽  
Lokesh Mohan ◽  
...  
Keyword(s):  
Barrier Height ◽  
Ideality Factor ◽  
Schottky Diodes ◽  
Reverse Current ◽  
X Ray Diffraction ◽  
Insulator Layer ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Sapphire Substrates ◽  
Contact Metal

ABSTRACTGallium nitride (n-type) films of thickness 300nm were grown on c-plane sapphire substrates using plasma assisted molecular beam epitaxy (PA-MBE). High resolution X-ray diffraction and photoluminescence measurements were used to confirm the crystalline and optical qualities of the grown films. Metal-semiconductor Schottky diodes were fabricated using Pt as the Schottky metal and Al as the Ohmic metal contact. Metal-insulator-semiconductor Schottky diodes were also fabricated using HfO2 (10nm) as the insulator material. Diode parameters like barrier height and ideality factor were extracted from I-V measurements. Introduction of HfO2 as the insulator layer leads to better rectifying behavior (forward to reverse current ratio improves from 5.1 to 8.9) with a reduction in reverse leakage current (by 7.4 times), increase in barrier height (from 0.62eV to 0.74eV) and a reduction in ideality factor (from 6 to 4.1) of the Schottky diode.

scholarly journals Frequency and Voltage-dependent Electrical Parameters, Interface Traps, and Series Resistance Profile of Au/(NiS:PVP)/n-Si Structures 

2021 ◽  
Author(s):  
Murat Ulusoy ◽  
Ş. Altındal ◽  
Perihan Durmuş ◽  
Süleyman Özçelik ◽  
Yashar Azizian Kalandaragh
Keyword(s):  
Series Resistance ◽  
Relaxation Times ◽  
Low Frequency ◽  
Surface States ◽  
Interface Layer ◽  
Voltage Profile ◽  
Electrical Parameters ◽  
Doping Density ◽  
Insulator Layer ◽  
Layer Width

Abstract A thin (NiS-doped PVP) interface layer was spin-coated on n-Si substrate and between Au contact were prepared on the surface by the sputtering method and then their basic electrical features for example diffusion-potential (VD), doping density of donor-atoms (ND), Fermi-energy (EF), barrier-height (ΦB), and depletion layer-width (WD) were extracted reverse-bias C-2-V plots as function frequency and voltage. The voltage profile of interface/surface-states (Nss)/ relaxation-times (τ), and series resistance (Rs) were also obtained from the admittance and Nicollian-Brews method, respectively. Strongly frequency-dependent and voltage especially in both accumulation and depletion regions due to the existence of Nss, Rs, and polarization as well as (NiS-doped PVP) organic interlayer. At low frequency, the observed higher value of C and G shows that thin (NiS:PVP) interlayer can be successfully used to obtain high charges/energy storage (MPS) structure/capacitor instead of conventional insulator layer performed traditional methods. As a result, the observed important changes in electrical parameters with frequency and voltage depend on Nss, their t, Rs, organic interlayer, and interfacial or dipole polarization.

P+ implanted 6H-SiC n+-i-p diodes: evidence for a post-implantation-annealing dependent defect activation

2014 ◽  
Vol 1693 ◽  
Author(s):  
R. Nipoti ◽  
M. Puzzanghera ◽  
F. Moscatelli
Keyword(s):  
Activation Energy ◽  
Temperature Dependence ◽  
Ideality Factor ◽  
Low Voltage ◽  
Reverse Current ◽  
Forward Current ◽  
Current Region ◽  
Recombination Centers ◽  
Energy Dependent ◽  
Post Implantation

ABSTRACTTwo n+-i-p 6H-SiC diode families with P+ ion implanted emitter have been processed with all identical steps except the post implantation annealing: 1300°C/20min without C-cap has been compared with 1950°C/10min with C-cap. The analysis of the temperature dependence of the reverse current at low voltage (-100V) in the temperature range 27-290°C shows the dominance of a periphery current which is due to generation centers with number and activation energy dependent on the post implantation annealing process. The analysis of the temperature dependence of the forward current shows two ideality factor n region, one with n = 1.9/2 at low voltage and the other one with 1 < n < 2 without passing through 1 for increasing voltages. For both the diode families the current with n = 1.9/2 is a periphery current due to recombination centers with a thermal activation energy near the 6H-SiC mid gap. In the forward current region of 1 < n < 2, the two diode families show different ideality factor values which could be attributed to a different post implantation annealing defect activation.

Current-transport mechanism in Au/V-doped PVC+TCNQ/p-Si structures

2015 ◽  
Vol 29 (13) ◽  
pp. 1550076 ◽  
Author(s):  
H. Tecimer ◽  
Ö. Vural ◽  
A. Kaya ◽  
Ş. Altındal
Keyword(s):  
Temperature Coefficient ◽  
Transport Mechanism ◽  
Forward Bias ◽  
Thermionic Emission ◽  
Negative Temperature ◽  
Positive Temperature ◽  
Current Transport ◽  
Insulator Layer ◽  
Zero Bias ◽  
Current Transport Mechanism

The forward and reverse bias current–voltage (I–V) characteristics of Au/V-doped polyvinyl chloride+Tetracyanoquino dimethane/porous silicon (PVC+TCNQ/p-Si) structures have been investigated in the temperature range of 160–340 K. The zero bias or apparent barrier height (BH) (Φ ap = Φ Bo ) and ideality factor (n ap = n) were found strongly temperature dependent and the value of n ap decreases, while the Φ ap increases with the increasing temperature. Also, the Φ ap versus T plot shows almost a straight line which has positive temperature coefficient and it is not in agreement with the negative temperature coefficient of ideal diode or forbidden bandgap of Si (α Si = -4.73×10-4 eV/K ). The high value of n cannot be explained only with respect to interfacial insulator layer and interface traps. In order to explain such behavior of Φ ap and n ap with temperature, Φ ap Versus q/2kT plot was drawn and the mean value of (Φ Bo ) and standard deviation (σs) values found from the slope and intercept of this plot as 1.176 eV and 0.152 V, respectively. Thus, the modified ( ln (Io/T2)-(qσs)2/2(kT)2 versus (q/kT) plot gives the Φ Bo and effective Richardson constant A* as 1.115 eV and 31.94 A ⋅(cm⋅K)-2, respectively. This value of A*( = 31.94 A⋅( cm ⋅K)-2) is very close to the theoretical value of 32 A ⋅(cm⋅K)-2 for p-Si. Therefore, the forward bias I–V–T characteristics confirmed that the current-transport mechanism (CTM) in Au/V-doped PVC+TCNQ/p-Si structures can be successfully explained in terms of the thermionic emission (TE) mechanism with a Gaussian distribution (GD) of BHs at around mean BH.

Shallow P+-N Junction Fabrication by Plasma Immersion Ion Implantation

1991 ◽  
Vol 223 ◽  
Author(s):  
C. A. Pico ◽  
X. Y. Qian ◽  
E. Jones ◽  
M. A. Lieberman ◽  
N. W. Cheung
Keyword(s):  
Ion Implantation ◽  
Ideality Factor ◽  
High Frequency ◽  
Cyclotron Resonance ◽  
High Field ◽  
Electron Cyclotron Resonance ◽  
Forward Bias ◽  
Electron Cyclotron ◽  
Significant Damage ◽  
Plasma Immersion Ion Implantation

ABSTRACTPlasma immersion ion implantation (PIII) has been applied to fabricate shallow p-n junction diodes and MOS test structures. BF3 ions created by an electron cyclotron resonance source were implanted into n-type Si(100) at an accelerating voltage of −2 kv. The implant doses ranged from 4 × 1014/cm2 to 4 × 1015/cm2. In some cases, the top layers of the Si(100) substrates were preamorphized by a 3 × 1015/cm2 to 1016/cm2 implant of SiF4 by PIII at −7.2 kV prior to the BF3 implant. The ideality factor exhibited in both non- and preamorphized samples during forward bias is 1.02 to 1.05. Reverse leakages were measured at 30 nA/cm2 at −5V. High frequency capacitance and high field breakdown measurements of the oxide test structures showed no significant damage to the oxide.

Improvement of the Refractory Metal/n-GaAs Interface by Low Temperature Anneal

1996 ◽  
Vol 448 ◽  
Author(s):  
A. Singh ◽  
L. Velásquez
Keyword(s):  
Ideality Factor ◽  
Forward Bias ◽  
Rf Sputtering ◽  
Frequency Dispersion ◽  
Interface States ◽  
Frequency Variation ◽  
Saturation Current ◽  
Zero Bias ◽  
Heat Treated ◽  
Schottky Junctions

AbstractThe W/n-GaAs Schottky junctions A and B of area 1.75×l0-2 cm2 were fabricated by deposition of W on the chemically etched polished surfaces of n-GaAs samples by rf sputtering using a rf powers of 300 Watt for 30 min. The W contact B was subjected to a 90 min. thermal anneal at 390 °C. The room temperature I-V and C-V/f (with 200 Hz < f < 1 MHz) measurements were carried out for both the as-deposited and thermally annealed W/n-GaAs Schottky junctions A and B, respectively. From the direct I-V data, the values of 1.09 and 8.1×10-8 A for the ideality factor (n) and the reverse saturation current (Io), respectively, were estimated for the diode B, compared to the values of n=1.70 and Io=6.3×10-6 A for the diode A. The observed frequency dispersion in the zero bias capacitance in the diode B was attributed to fast interface states with a time constant, τ2=6 μs and density, Nss2=5.8×1010 eV-1cm-2, whereas, both the slow interface states (with τ1=4 ms and density, Nss1=7.8×1012 eV-1cm-2) and fast states (with τ2=1 μs and density Nss2=8.6×1010 eV-1cm-2) were responsible for the observed frequency variation of the zero bias capacitance in the diode A. For the forward bias values in the range 20-100 mV, the frequency dispersion in the measured capacitance suggested the presence of both the fast and slow interface states (with time constants differing by three orders of magnitude) in the as-deposited and the heat treated W/n-GaAs interfaces. Thermal anneal at 390 °C for 90 min. lowered the density of states at the W/n-GaAs interface by two orders of magnitude and resulted in the formation of a high quality rectifying W contact to n-GaAs with a rectification ratio of 1.4×104, a low Io and an ideality factor close to unity.

Al+ Implanted 4H-SiC p+-i-n Diodes: Evidence for Post-Implantation-Annealing Dependent Defect Activation

2014 ◽  
Vol 778-780 ◽  
pp. 657-660 ◽  
Author(s):  
Ulrike Grossner ◽  
Francesco Moscatelli ◽  
Roberta Nipoti
Keyword(s):  
Activation Energy ◽  
Ideality Factor ◽  
Reverse Current ◽  
Activation Energies ◽  
Forward Current ◽  
Current Voltage ◽  
Different Temperatures ◽  
Current Voltage Characteristics ◽  
The One ◽  
Post Implantation

Two families of Al+implanted vertical p+in diodes that have been processed all by identical steps except the post implantation annealing one have been characterized with current voltage measurements from -100 to +5V at different temperatures. Analysis of the static forward current voltage characteristics shows two different ideality factor regions, which are distinct for each family. The reverse current voltage characteristics reveals corresponding two different activation energies. These are assumed to be correlated to the Z1/2defect for the one case and another one with an activation energy of 0.25eV.

ELECTRICAL PROPERTIES OF Al/p-Si STRUCTURE WITH Al2O3 THIN FILM FABRICATED BY ATOMIC LAYER DEPOSITION SYSTEM

2016 ◽  
Vol 24 (06) ◽  
pp. 1750077
Author(s):  
DILBER ESRA YİLDİZ ◽  
HATICE KANBUR CAVUŞ
Keyword(s):  
Atomic Layer Deposition ◽  
Barrier Height ◽  
Image Force ◽  
Atomic Layer ◽  
State Density ◽  
Mis Structure ◽  
Insulator Layer ◽  
Zero Bias ◽  
Energy Density Distribution ◽  
Layer Deposition

Al2O3 insulator layer was deposited by atomic layer deposition (ALD) technique on p-type Si [Formula: see text] and the Al/Al2O3/p-Si metal/insulator/semiconductor (MIS) structures were fabricated. The current–voltage ([Formula: see text]) characteristics of these structures were investigated in two different temperatures. The main electrical parameters such as the ideality factor ([Formula: see text]), zero bias barrier height ([Formula: see text]), and series resistance ([Formula: see text]) values were found for 300 and 400[Formula: see text]K. The energy density distribution profiles of the interface state density ([Formula: see text]) were determined from the [Formula: see text] characteristics. In addition, the capacitance–voltage ([Formula: see text]) and conductance–voltage ([Formula: see text]) characteristics of devices were investigated in the frequency range 50–1000[Formula: see text]kHz at room temperature. Frequency-dependent electrical characteristics such as doping acceptor concentration ([Formula: see text]), energy difference between the valance band edge and bulk Fermi level ([Formula: see text]), diffusion potential ([Formula: see text]), barrier height ([Formula: see text]), the image force barrier lowering ([Formula: see text]), maximum electric field ([Formula: see text]), and [Formula: see text] values were determined using [Formula: see text] and [Formula: see text] plots. In addition, the [Formula: see text] values were performed using Hill–Coleman method. According to experimental results, the locations of [Formula: see text] and [Formula: see text] have an important effect on [Formula: see text], [Formula: see text] and [Formula: see text] plots of MIS structure.

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