A STUDY ON DIVERSE NANOSTRUCTURE FOR IMPLEMENTING LOGIC GATE DESIGN FOR QCA

Quantum dot cellular automata (QCA) define the nanostructure of basic computer. It is used as an alternative for designing high-speed computer over CMOS technology. The basic logic in QCA is the logic state that does not measure with voltage level; rather it measures the polarity of electrons in cell. The Majority Voter (MV) is first introduced to design the logic circuits, but only using MV, designing complex logic circuit became inefficient. Many proposals had been made for designing QCA logic gate. In this paper we focus on different useful nanostructures, reduced size and efficient design of Nand–Nor Inverter (NNI), 3 × 3 tile structures for implementing NNI, And–Or Logic, and AOI also present logic synthesis using proposed gates. We analyze QCA defect on proposed gates and describe its permissible defect tolerance. In QCA we describe application for implementing standard functions using proposed structures in this paper and describe effective area of proposed structures.

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Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

Journal of Circuits System and Computers ◽

10.1142/s021812661750030x ◽

2016 ◽

Vol 26 (02) ◽

pp. 1750030 ◽

Cited By ~ 3

Author(s):

Pankaj Kumar ◽

Rajender Kumar Sharma

Keyword(s):

Signal Processing ◽

Low Power ◽

High Speed ◽

Digital Signal ◽

Cmos Technology ◽

Two Dimensional ◽

Efficient Design ◽

Parallel Multiplier ◽

Power Delay Product ◽

Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

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FPGA Data Acquisition of Electrical Parameter

European Journal of Engineering and Technology Research ◽

10.24018/ejers.2021.6.4.1538 ◽

2021 ◽

Vol 6 (4) ◽

pp. 105-123

Author(s):

Kennedy Ahamefula Iroanusi

Keyword(s):

Data Acquisition ◽

Personal Computer ◽

High Speed ◽

Electrical Parameter ◽

Logic Gate ◽

System On Chip ◽

Circuit Board ◽

Sensor Data ◽

Voltage Level ◽

On Chip

A data acquisition system using a Programmable Logic Gate Array (FPGA) and Graphical User Interface (GUI) for visual enhancement designed for Personal Computer is shown. The data acquisition of voltage (V), current (A) and temperature ( ) signals and/or parameters transmitted at high frequency in real time via the system-on-chip (SOC) created on Spartan 6 FPGA. The system-on-chip is achieved by programming the FPGA with a high-speed hardware description language (Verilog) code written for the system, Printed Circuit Board (PCB) was designed for the system and the GUI has been created using a graphical approach utilizing LabVIEW to enable data monitoring on Personal Computer (PC) display. The FPGA requires digital input signals; therefore, an analogue to digital convertor (ADC) is required for the convert sensor data from analogue signal from sensors to digital signals. A voltage level shifter is required to normalise the voltage level standards within the circuity in between the 5V from the ADC converter and the 3.3V voltage requirement for the FPGA. The Spartan 6 FPGA receives data from the analogue sensors via the ADC, the data are wrapped up in packets and transmitted through RS-232 serial port to the PC. The three aforementioned parameters are monitored on the GUI on the PC presented in both numerical and graphical format and all data can be store in a file for backup storage, maintenance or reference purposes.

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Synthesis of composite logic gate in QCA embedding underlying regular clocking

Facta universitatis - series Electronics and Energetics ◽

10.2298/fuee2101115p ◽

2021 ◽

Vol 34 (1) ◽

pp. 115-131

Author(s):

Jayanta Pal ◽

Dhrubajyoti Bhowmik ◽

Ayush Singh ◽

Apu Saha ◽

Bibhash Sen

Keyword(s):

Symmetric Functions ◽

Logic Gate ◽

Logic Gates ◽

Cmos Technology ◽

Dissipated Energy ◽

Circuit Realization ◽

Alternative Technologies ◽

Gate Count ◽

Majority Voter ◽

Cost Efficient

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

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Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

Circulation in Computer Science ◽

10.22632/ccs-2017-251-50 ◽

2017 ◽

Vol 2 (2) ◽

pp. 15-19 ◽

Cited By ~ 3

Author(s):

Md. Saud Al Faisal ◽

Md. Rokib Hasan ◽

Marwan Hossain ◽

Mohammad Saiful Islam

Keyword(s):

High Speed ◽

Field Effect Transistors ◽

Cmos Technology ◽

Channel Length ◽

Capacitive Coupling ◽

Oxide Semiconductor ◽

Double Gate ◽

Short Channel ◽

Channel Effects ◽

Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

Applied Sciences ◽

10.3390/app11010429 ◽

2021 ◽

Vol 11 (1) ◽

pp. 429

Author(s):

Min-Su Kim ◽

Youngoo Yang ◽

Hyungmo Koo ◽

Hansik Oh

Keyword(s):

Integrated Circuits ◽

Embedded System ◽

Low Power ◽

High Speed ◽

Cmos Technology ◽

Clock Frequency ◽

Clock Generation ◽

Allocation Method ◽

Evaluation Board ◽

28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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