scholarly journals Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Peter Nilsson
Keyword(s):  
Power Consumption ◽  
Cmos Technology ◽  
Fir Filter ◽  
Power Ratio ◽  
Iir Filters ◽  
Nanoscale Cmos ◽  
Iir Filter ◽  
Different Types ◽  
Static Power ◽  
Bit Serial

This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely, bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative power ratio is strongly dependent on the used word length; that is, the gain in power ratio is larger for longer word lengths. A static power ratio at 0.48 is shown for the bit-serial FIR-filter and a power ratio at 0.11 is shown in the arithmetic part of the FIR-filter. The static power ratio in the IIR-filter is 0.36 in the bit-serial filter and 0.06 in the arithmetic part of the filter. It is also shown that the use of storage, such as registers, relatively the arithmetic part, affects the power ratio. The relatively lower power consumption in the IIR-filter compared to the FIR-filter is due to the lower use of registers.

scholarly journals Efficient uniform digital filter bank with linear phase and FRM technique for hearing aids

2018 ◽  
Vol 7 (1.9) ◽  
pp. 69 ◽  
Author(s):  
G Parameshappa ◽  
D Jayadevapp
Keyword(s):  
Digital Filter ◽  
Hearing Aids ◽  
Filter Bank ◽  
Fir Filter ◽  
Linear Phase ◽  
Iir Filters ◽  
Iir Filter ◽  
Band Filter ◽  
Frequency Response Masking ◽  
Digital Filter Bank

This paper attempts to present an uniform digital filter bank based on linear phase FIR and IIR filters applied for Frequency Response Masking (FRM) technique in hearing aid applications.In the proposed filter bank, nine uniformly spaced sub-bands are formed with the help of half band filters and masking filters. These nine channel FIR filter bank is realized using an interpolated half band linear phase FIR filter and an appropriate number of masking FIR filters. The nine channel IIR filter bank is realized using an interpolated half band approximately linear phase IIR filter and an appropriate number of masking filters. The proposed approximately linear phase IIR half band filter bank is compared with filter bank based on linear phase FIR half band filters in terms of area, power, memory and number of gates needed for implementation. The experiment was carried on various hearing loss cases and the results obtained from these tests proves that, the proposed filter bank achieved the required matching between audiograms and magnitude response of the filter bank at very reasonable range with less computational complexity.

Multirate Techniques in Filter Design and Implementation

2009 ◽  
pp. 274-294
Author(s):  
Ljiljana Milic
Keyword(s):  
Digital Filters ◽  
Filter Design ◽  
Fir Filter ◽  
Single Stage ◽  
Sharp Transition ◽  
Filter Length ◽  
Iir Filters ◽  
Iir Filter ◽  
Design And Implementation ◽  
Promising Solution

Digital filters with sharp transition bands are difficult, sometimes impossible, to be implemented using single-stage structures. A serious problem with a single-stage sharp FIR filter is its complexity. The FIR filter length is inversely proportional to the transition–width and complexity becomes prohibitively high for sharp filters, (Lim, 1986). IIR filters with sharp transition bands suffer from extremely high sensitivities of transfer function poles. In many practical cases, the multirate approach is the promising solution that could be applied for implementation of a sharp FIR or IIR filter. In this chapter, we present two methods for designing filters having narrow transition bandwidths: multistage filtering suitable for narrowband filters, and the method based on multirate and complementary filtering, which may be used for filters of arbitrary bandwidths.

scholarly journals Design of High Performance Decoder with Mixed Logic Styles

2018 ◽  
Vol 7 (2.20) ◽  
pp. 119
Author(s):  
Mohammad Khadir ◽  
S Renukarani ◽  
Tunikipati Usharani ◽  
D Hemanth Kumar
Keyword(s):  
Time Delay ◽  
Power Consumption ◽  
High Power ◽  
High Performance ◽  
Cmos Technology ◽  
Combinational Circuits ◽  
Framework Design ◽  
Different Types ◽  
Portable Technology ◽  
Low Performance

The CMOS technology is the mostly portable technology used in the designing of the circuits and in its fabrication. Designing of the circuits using CMOS technology requires the high power, high transistors count and low performance. The basic idea of the project is in order to reduce the count of transistors, time delay, and power consumption and to increase the performance of the circuits such as line decoders. The line decoder is a combinational circuits to which „n‟ no .of inputs are given as input and the output is 2^n based on the selected input and it requires 20 and more than 20 transistors to design any MxN decoders using CMOS technology .In order to configure the parameters and to make it more portable we are using different types of logic styles this usage of technologies more than one technologies on each circuit is a mixed logic styles .In this concept we observe the results as per required .The technologies we use in this is TGL/DVL. The suggested framework “Design about low Power, helter execution 2-4 What's more 4-16 blended rationale offering Decoders” is executed done 45nm engineering utilizing cadence virtuoso tool. The circuit schematic is designed and the circuits are simulated for functionality verification.  

Low computation digital down converter using polyphase IIR filter

Circuit World ◽  
2019 ◽  
Vol 45 (3) ◽  
pp. 169-178 ◽  
Author(s):  
Hiren K. Mewada ◽  
Jitendra Chaudhari
Keyword(s):  
Group Delay ◽  
Filter Design ◽  
Fir Filter ◽  
Linear Phase ◽  
Content Type ◽  
Iir Filters ◽  
Iir Filter ◽  
Alternative Option ◽  
Digital Down Converter ◽  
Sample Rate

Purpose The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter. Design/methodology/approach Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC. Findings The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption. Originality/value The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.

Nonvolatile, Spin-Based, and Low-Power Inexact Full Adder Circuits for Computing-in-Memory Image Processing

SPIN ◽  
2019 ◽  
Vol 09 (03) ◽  
pp. 1950013 ◽  
Author(s):  
Abdolah Amirany ◽  
Ramin Rajaei
Keyword(s):  
Image Processing ◽  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Structural Similarity ◽  
Full Adder ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Approximate Computing ◽  
Static Power

Deep submicron conventional complementary metal oxide semiconductor (CMOS) technology is facing various issues such as high static power consumption due to the increasing leakage currents. In recent years, spin-based technologies like magnetic tunnel junctions (MTJ) have emerged and shown some fascinating features to overcome the aforesaid issues of CMOS technology. The hybrid MTJ/CMOS circuits offer low power consumption, nonvolatility, and high performance. This paper proposes two novel hybrid MTJ/CMOS approximate full-adder circuits (AXMA) for low power approximate computing-in-memory architectures. The proposed AXMAs offer low area, high sensing speed, considerable lower energy consumption, and the lowest power delay product (PDP) than the considered antecedent counterparts. The proposed AXMAs also introduce the advantage of full nonvolatility to the systems. This feature allows the system to be powered off during the idle modes in order to reduce the static power without the need for any retention parts or loss of data. Applications of the proposed AXMAs in digital image processing and their effect on the quality of images considering some relevant metrics like peak signal-to-noise ratio (PSNR) and mean structural similarity (MSSIM) are also investigated using the MATLAB software.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

CMOS PULSE GENERATOR FOR BPSK, OOK, PAM, AND PPM MODULATIONS

2009 ◽  
Vol 18 (03) ◽  
pp. 487-495 ◽  
Author(s):  
VINCENZO STORNELLI ◽  
GIUSEPPE FERRI ◽  
KING PACE
Keyword(s):  
Remote Control ◽  
Power Consumption ◽  
Pulse Duration ◽  
Short Range ◽  
Pulse Generator ◽  
Supply Voltage ◽  
Pulse Repetition Frequency ◽  
Cmos Technology ◽  
Single Chip ◽  
Control Applications

This work presents a single chip integrated pulse generator-modulator to be utilized in a short range wireless radio sensors remote control applications. The circuit, which can generate single pulses, modulated in BPSK, OOK, PAM, and also PPM, has been developed in a standard CMOS technology (AMS 0.35 μm). Typical pulse duration is about 1 ns while pulse repetition frequency is until 200 MHz (5 ns "chip" time). The operating supply voltage is ± 2.5 V, while the whole power consumption is about 15 mW. Post-layout parametric and corner analyses have confirmed the theoretical expectations.

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