scholarly journals Design of High Performance Decoder with Mixed Logic Styles

2018 ◽  
Vol 7 (2.20) ◽  
pp. 119
Author(s):  
Mohammad Khadir ◽  
S Renukarani ◽  
Tunikipati Usharani ◽  
D Hemanth Kumar
Keyword(s):  
Time Delay ◽  
Power Consumption ◽  
High Power ◽  
High Performance ◽  
Cmos Technology ◽  
Combinational Circuits ◽  
Framework Design ◽  
Different Types ◽  
Portable Technology ◽  
Low Performance

The CMOS technology is the mostly portable technology used in the designing of the circuits and in its fabrication. Designing of the circuits using CMOS technology requires the high power, high transistors count and low performance. The basic idea of the project is in order to reduce the count of transistors, time delay, and power consumption and to increase the performance of the circuits such as line decoders. The line decoder is a combinational circuits to which „n‟ no .of inputs are given as input and the output is 2^n based on the selected input and it requires 20 and more than 20 transistors to design any MxN decoders using CMOS technology .In order to configure the parameters and to make it more portable we are using different types of logic styles this usage of technologies more than one technologies on each circuit is a mixed logic styles .In this concept we observe the results as per required .The technologies we use in this is TGL/DVL. The suggested framework “Design about low Power, helter execution 2-4 What's more 4-16 blended rationale offering Decoders” is executed done 45nm engineering utilizing cadence virtuoso tool. The circuit schematic is designed and the circuits are simulated for functionality verification.  

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

LOW POWER AND HIGH PERFORMANCE SINGLE-ENDED SENSE AMPLIFIER

2013 ◽  
Vol 22 (07) ◽  
pp. 1350062 ◽  
Author(s):  
AJAY KUMAR SINGH ◽  
MAH MENG SEONG ◽  
C. M. R. PRABHU
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Voltage Drop ◽  
Cmos Technology ◽  
Power Efficient ◽  
Sense Amplifier ◽  
Current Voltage ◽  
Direct Current Voltage ◽  
Voltage Conversion ◽  
Lower Voltage

This paper presents a new power efficient single ended sense amplifier (SA). The proposed circuit is based on the direct current voltage conversion technique. It has been simulated using Microwind3 and DSCH3 tools (advanced BSIM 4 level) for 90 nm CMOS technology in terms of power consumption, sense time and results were compared to other circuits. The proposed SA circuit consumes more than 50% less power and gives 90% faster sensing speed compared to other circuits. The lower power consumption is due to lower leakage current, lower voltage drop on bit-line and faster speed is due to positive feedback of the circuit. The proposed circuit is more robust against any process and temperature variation.

scholarly journals Optimizing the Performance of MOS Stacks

2020 ◽  
Vol 16 (1) ◽  
pp. 85-98
Author(s):  
Sherif Sharroush
Keyword(s):  
Time Delay ◽  
Power Consumption ◽  
Figure Of Merit ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Scaling Factor ◽  
Worst Case ◽  
In Series ◽  
High Transition ◽  
Exclusive Or

CMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters. Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN). The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances. The problem gets worse with increasing the number of inputs. In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined. The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area. The optimum scaling factor corresponding to the best performance is determined. It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay. The proposed figure of merit is evaluated for different cases with the results discussed. The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.

scholarly journals Energy Efficient SRAM

2019 ◽  
Vol 8 (9) ◽  
pp. 1086-1091
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Static Noise Margin ◽  
Noise Margin ◽  
And Performance ◽  
The Stability ◽  
Static Noise

Memories are an essential unit of any digital circuit, thus their power consumption must be considered during the designing process of the cells. To improve performance, reduce delay and increase stability, it is advisable to decrease the power consumed by the memory. Due to high demand of speed, high performance, there’s a need to decrease the size of the device, thereby increasing the devices placed per chip. This high integration makes chips more complex but improves device performance. Design of SRAM cells with speed and low power is crucial so as to replace DRAMs. The layout of SRAM has advanced to meet the requirements of the present industry in accordance with parameters like delay, power consumption and stability etc. This paper presents the aim of analyzing different technologies used to make SRAM more efficient in terms of parameters such as static noise margin, latency and dissipation of power. The stability investigation of SRAM cells are usually derived from the Static Noise Margin (SNM) analysis. Here we observe a SRAM design which has used dynamic logic and pass transistor logic. We further study the effects made on this design by employing various technologies such as AVL-S, AVL-G, AVL and MT-CMOS, at 180nm CMOS technology to achieve enhancements in delay, power consumption and performance. The proposed circuits are simulated and the results obtained have been analyzed to show significant improvement over conventional SRAM designs. Cadence Virtuoso simulation is used to confirm all the results obtained in this paper for the simulation of 180 nm CMOS technology SRAMs.

DESIGN AND ANALYSIS OF A NOVEL LOW PDP FULL ADDER CELL

2011 ◽  
Vol 20 (03) ◽  
pp. 439-445 ◽  
Author(s):  
M. H. GHADIRY ◽  
ABU KHARI A'AIN ◽  
M. NADI S.
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Accurate Analysis ◽  
And Performance ◽  
Full Swing ◽  
Driving Capability

This paper, presents a new full-swing low power high performance full adder circuit in CMOS technology. It benefits from a full swing XOR-XNOR module with no feedback transistors, which decreases delay and power consumption. In addition, high driving capability of COUT module and low PDP design of SUM module contribute to more PDP reduction in cascaded mode. In order to have accurate analysis, the new circuit along with several well-known full adders from literature have been modeled and compared with CADENCE. Comparison consists of power consumption, performance, PDP, and area. Results show that there are improvements in both power consumption and performance. This design trades area with low PDP.

scholarly journals Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Peter Nilsson
Keyword(s):  
Power Consumption ◽  
Cmos Technology ◽  
Fir Filter ◽  
Power Ratio ◽  
Iir Filters ◽  
Nanoscale Cmos ◽  
Iir Filter ◽  
Different Types ◽  
Static Power ◽  
Bit Serial

This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely, bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative power ratio is strongly dependent on the used word length; that is, the gain in power ratio is larger for longer word lengths. A static power ratio at 0.48 is shown for the bit-serial FIR-filter and a power ratio at 0.11 is shown in the arithmetic part of the FIR-filter. The static power ratio in the IIR-filter is 0.36 in the bit-serial filter and 0.06 in the arithmetic part of the filter. It is also shown that the use of storage, such as registers, relatively the arithmetic part, affects the power ratio. The relatively lower power consumption in the IIR-filter compared to the FIR-filter is due to the lower use of registers.

scholarly journals A Power Efficient Improved NOR-Type TCAM Design using OR-Type Match-Line Segment

2020 ◽  
Vol 8 (6) ◽  
pp. 4885-4890
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Cmos Technology ◽  
The Novel ◽  
Metal Gate ◽  
Power Efficient ◽  
Content Addressable Memory ◽  
Ternary Content Addressable Memory ◽  
High K

This paper presents the novel way to deal with diminish power utilization in a ternary content addressable memory (TCAM) designed in current innovation. The main aim of this TCAM design is to reduce the dynamic power consumption. In TCAM large amount of the power consumption happens during search operation, so we focussed on this area. Here right now give pragmatic plan of a TCAM which is arranged for low-power applications. Simulation of this design has done in Tanned EDA V.16 tool. For simulations of Low power TCAM designs we used predictive technology model (PTM) 45nm for high-performance applications which include metal gate, high-k and stress impact of CMOS technology.

scholarly journals Buried Powered 4t Sram with Improved Write Margin

2020 ◽  
Vol 9 (3) ◽  
pp. 2348-2351
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Cmos Technology ◽  
Sram Cell

The main intention of this paper is to understand clearly about the high performance of 4T-SRAM with an improved write margin. the power consumption is often reduced considerably by using a buried power rail (BPR) to the SRAM cell, which reduces the resistance of bit line and word line. The write margin is often increased by the fine standardization of metal dimensions within the SRAM cell. Conventionally, 4T-SRAM cell offers high speed and fewer space compared to 6T-SRAM cell. 4T-SRAM is actualized using 130nm CMOS Technology.

A Compact High-Performance 10-bit 30-Channel OLED Driver Using Switched Capacitor Circuit for High-Linearity Application

2021 ◽  
pp. 2250013
Author(s):  
Neeru Agarwal ◽  
Neeraj Agarwal ◽  
Chih-Wen Lu
Keyword(s):  
Power Consumption ◽  
Output Voltage ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Cmos Technology ◽  
Settling Time ◽  
Switched Capacitor ◽  
Voltage Range ◽  
High Output Voltage

This work proposes a new OLED driver architecture with 10-bit segmented DAC and switched capacitor multiply-by-two circuit application. A 30-channel 10-bit switched capacitor driver chip prototype is implemented in 0.18-[Formula: see text]m CMOS technology. In this architecture, the achieved output range is 1.5–4.8[Formula: see text]V for an input range of 1.5–3.15[Formula: see text]V, which is suitable for OLED driver with different colors. This architecture is not only converting the digital input signal to analog output for the display panel but also giving amplified high output voltage range. In the segmented DAC, 6-bit coarse DAC and 4-bit fine DAC are used for the input voltage range 1.5–3.15[Formula: see text]V. In a conventional RDAC for the output voltage of 4.8[Formula: see text]V, it requires 2[Formula: see text] switches i.e., 14-bit RDAC for the same resolution. Hence, conventional RDAC driver is four times larger than the proposed innovative very compact and high speed 10-bit segmented DAC switched capacitor OLED driver. The new architecture drastically reduces the number of switches and complex metal routing which results in reduced power consumption and good settling time. In the proposed OLED driver, no extra buffer is required as switched capacitor op-amp is applied for the same purpose with a gain of more than one. This high-resolution design with small die area also improves the linearity and uniformity with low-power consumption. The post-simulated results show that the OLED driver exhibits the maximum DNL and INL of 0.03 LSB and [Formula: see text]0.06 LSB, respectively, with an LSB voltage of 3[Formula: see text]mV. The one-channel area is 0.586[Formula: see text]mm [Formula: see text] 0.017[Formula: see text]mm and the settling time is 4.25[Formula: see text][Formula: see text]s for 30[Formula: see text]k[Formula: see text] and 30[Formula: see text]pF driving load.

A Survey of High Performance Cryptography Algorithms for WiMAX Applications Using SDR

2013 ◽  
pp. 231-246 ◽  
Author(s):  
Rafidah Ahmad ◽  
Widad Ismail
Keyword(s):  
Power Consumption ◽  
High Power ◽  
Software Defined Radio ◽  
High Performance ◽  
Processing Time ◽  
Ieee 802.16 ◽  
Advanced Encryption Standard ◽  
Wireless Broadband ◽  
High Power Consumption ◽  
Design Cost

As wireless broadband technology has become very popular, the introduction of Worldwide Interoperability for Microwave Access (WiMAX) based on IEEE 802.16 standard has increased the demand for wireless broadband access in the fixed and the mobile devices. This development makes wireless security a very serious concern. Even though the Advanced Encryption Standard (AES) has been popularly used for protection in WiMAX applications, still WiMAX is exposed to various classes of wireless attack, such as interception, fabrication, modification, and reply attacks. The complexity of AES also produces high power consumption, long processing time, and large memory. Hence, an alternative cryptography algorithm that has a lower power consumption, faster and smaller memory, is studied to replace the existing AES. A Software Defined Radio (SDR) is proposed as a different way of proving the performance of the cryptography algorithm in real environments because it can be reprogrammed, which leads to design cost and time reductions.

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