scholarly journals Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power

2017 ◽  
Vol 7 (6) ◽  
pp. 3010
Author(s):  
Woo Wei Kai ◽  
Nabihah binti Ahmad ◽  
Mohamad Hairol Bin Jabbar
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Threshold Voltage ◽  
Average Power ◽  
Vlsi Design ◽  
Full Adder ◽  
Oxide Thickness ◽  
Conventional Technique ◽  
Body Biasing ◽  
Static Power

The static power consumption is an important parameter concern in IC design due to t for a higher integration numbers of transistor to achieve greater performance in a single chip. Leakage current is the main issues for static power dissipation in standby mode as the size of transistor been scale. Therefore, the subthreshold leakage current rises due to threshold voltage scaling and gate leakage current increases due to scale down of oxide thickness. In this paper, a Variable Body Biasing (VBB) technique was applied to reduce static power consumption in VLSI design. The VBB technique used a DC bias at body terminal to control the threshold voltage efficiently. The Synopsys Custom Designer EDA tools in 90nm MOSFET technology was used to design a 1-bit full adder with VBB technique in full custom methodology. The simulation of 1-bit full adder was carried out with operation voltage   supply was compared in conventional technique and VBB technique. The results achieved the reduction in term of peak power,   and average power,   in static CMOS 1-bit full adder compared with conventional bias and VBB technique.

scholarly journals Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology

2019 ◽  
Vol 14 (2) ◽  
pp. 912
Author(s):  
Woo Wei Kai ◽  
Nabihah Ahmad ◽  
Mohamad Hairol Jabbar
Keyword(s):  
Low Power ◽  
Average Power ◽  
Full Adder ◽  
Oxide Thickness ◽  
Low Complexity ◽  
Operating Voltage ◽  
Short Channel ◽  
Static Power ◽  
Subthreshold Leakage ◽  
Power Delay Product

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of  supply. The result showed the reduction of VBB technique in term of peak power,  and average power,   compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

scholarly journals Low-Power High-Speed Double Gate 1-bit Full Adder Cell

2016 ◽  
Vol 62 (4) ◽  
pp. 329-334 ◽  
Author(s):  
Raushan Kumar ◽  
Sahadev Roy ◽  
C.T. Bhunia
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Spice Simulation ◽  
Pass Transistor ◽  
Voltage Swing

Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

scholarly journals Implementing Static and Dynamic Full Adders in Dynamic Body Biasing Technology

2019 ◽  
Vol 8 (2) ◽  
pp. 498-502 ◽  
Keyword(s):  
Threshold Voltage ◽  
High Speed ◽  
New Technology ◽  
Full Adder ◽  
Cmos Technology ◽  
Dynamic Threshold ◽  
Body Biasing

In this paper, we proposed the new technology for good performance and high speed. We used dynamic body biasing implemented static and dynamic full adders. This is very useful for threshold voltage decrease by the dynamic body biasing which has good benefit for decrease delay of the circuits. The proposed method provides less power and delay. In Full Adder implementation CMOS technology at 180 nm is used. Simulation is done by cadence virtuoso tool. New static and dynamic Full Adders have been suggested in this paper. We have implemented 8 bit static and dynamic full adder in 180 nm Dynamic Threshold CMOS technology. The proposed DTMOS circuits are faster than existing Full Adder circuits.

A Survey on Low Power Design Approaches in nanoscale regime

2020 ◽  
Vol 12 ◽  
Author(s):  
Vijay Kumar Sharma
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Leakage Current ◽  
Threshold Voltage ◽  
Vlsi Design ◽  
Low Power Design ◽  
Technology Node ◽  
Reduction Techniques ◽  
The Individual ◽  
Technology Nodes

Background: The increased demand of battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality and faster response at lower technology nodes. The applied power supply and threshold voltage of the individual device is scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current. Objective: Leakage current should be made recessive with the continuous scaling of technology nodes. Methods: Various leakage current mitigation methods had been employed to reduce the leakage current at different abstraction levels. This review paper demonstrates the survey of systematic arrangement of device scaling, leakage power, its causes, and various methods to overcome the leakage current at circuit level design. Results: 3-input NAND (NAND3) gate is designed and simulated at 22 nm technology node on HSPICE tool and analyzed for comparison of different leakage reduction techniques. Conclusion: INDEP approach is the most effective approach to reduce the leakage current and improving the reliability of the circuits followed by DTCMOS technique as compared to other available techniques.

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

scholarly journals Effect of Body Biasing on 0.13 Um CMOS Transistor

2019 ◽  
Vol 9 (2) ◽  
pp. 3185-3189
Keyword(s):  
Metal Oxide ◽  
Leakage Current ◽  
Threshold Voltage ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Point ◽  
Optimum Operating ◽  
Common Source ◽  
Body Biasing

Complementary metal-oxide semiconductor (CMOS) consist of n-type metal-oxide semiconductor field effect transistor (NMOS) and p-type MOSFET (PMOS). In common practice, only three terminals of these transistors are used, namely gate, source and drain. Meanwhile, the fourth terminal, which is body terminal is tied to source. Changing body terminal bias causes the transistor to have a body effect. In this work, optimum body biasing for 0.13 µm NMOS and PMOS are identified. Effect of body biasing to the MOSFETs are investigated. In addition, how body biases affect CMOS circuits are also observed. Three type of body biasing are considered, namely Forward Body Biasing (FBB), Reverse Body Biasing (RBB), and Dynamic Threshold MOS (DTMOS). Drain current, Id versus gate voltage, VG and drain current, Id versus drain-source voltage, VDS for FBB, RBB and DTMOS are simulated to determine the optimum operating point for each biasing technique. To observe the effect of body biasing techniques on the circuits, inverter and common source amplifier are constructed using FBB, RBB and DTMOS. In addition, the circuits also constructed in zero body biasing (ZBB) for comparison. The results show that, optimum body biasing is at 0.6 V for all three body biasing techniques. FBB and DTMOS cause the threshold voltage, Vth to decrease but increase the leakage current. On the other hand, RBB causes increase in threshold voltage, Vth yet reduces the leakage current of the CMOS. The results obtained in this work will enable other circuit designers to determine the optimum FBB, RBB and DTMOS operating point.

scholarly journals Design of Advanced 64-bit Full Adder in 45-nm Technology

2019 ◽  
Vol 8 (4) ◽  
pp. 12173-12178
Keyword(s):  
Power Consumption ◽  
Average Power ◽  
Full Adder ◽  
The Other ◽  
Performance Parameters ◽  
Average Power Consumption ◽  
Transmission Gates

This paper presents the design of a 64-bit parallel adder with 45_nm technology using cadence virtuoso tool. The proposed method uses the designed 1-bti full adder and the performance is compared with the other cadence virtuoso technologies i.e. 180-nm and 90-nm. Performance parameters such as average power, delay, PDP and transistor count are calculated and compared with the 180-nm and 90-nm technologies. The proposed method based on 45-nm technology at 1V supply exhibits the average power consumption as low as 0.114µW and less delay of 3.503ps which is obtained from the absorption of extremely feeble CMOS inverters together with physically powerful transmission gates. The full adder is designed by using XNOR module and transmission gates. The XNOR module is used to produce the output SUM and the transmission gates are used to produce the output Carryout.

Static Power Consumption: Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistor

2007 ◽  
Author(s):  
Uthaman Raju ◽  
Praveen Pandojirao-S. ◽  
Niraja Sivakumar ◽  
Dereje Agonafer
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
High Performance ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Design Parameters ◽  
Gate Length ◽  
Good Tool ◽  
Soi Mosfet ◽  
Static Power

The static power consumption due to leakage current plays a significant part in semiconductor devices, as the device dimensions continue to shrink. Low power dissipation is one of the critical factors needed to achieve high performance in a chip. New methods are continuously being implemented for reduction of leakage current in deep sub micron ultra thin SOI MOSFET using device simulator tools. In this paper, an 18nm gate length ultra thin SOI MOSFET is simulated for different silicon body thicknesses and the leakage current is determined by using the device simulator, MEDICITM. It is demonstrated that MEDICI™ device simulations is a good tool that can effectively be used for ultra thin SOI MOSFET devices to study the effect of design parameters on the leakage current. Ultra thin SOI MOSFET with 18nm gate length of different Silicon body thickness is simulated and the leakage current as determined by using MEDICI™ shows that the leakage current decreases by 10–15% as the silicon body thickness reduces by 2 nm.

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