scholarly journals Improved Frequency Compensation Technique for Three-Stage Amplifiers

2021 ◽  
Vol 11 (1) ◽  
pp. 11
Author(s):  
Alejandro Roman Loera ◽  
Anurag Veerabathini ◽  
Luis Alejandro Flores Oropeza ◽  
Luis Antonio Carrillo Martínez ◽  
David Moro Frias
Keyword(s):  
Detailed Comparison ◽  
Cmos Process ◽  
Slew Rate ◽  
Compensation Scheme ◽  
Frequency Compensation ◽  
Output Node ◽  
Miller Compensation ◽  
Compensation Technique ◽  
Simulation Results ◽  
Nested Miller Compensation

Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and reduced settling time. The proposed compensation uses an auxiliary feedback to increase the total effective compensation capacitance without loading the output node. The proposed compensation scheme is validated in simulation by implementing a three-stage amplifier driving 10 pF load capacitor in a 0.18 μm CMOS process. A detailed comparison of the compensation with a conventional nested Miller compensation is also presented. The simulation results showed a reduction in total compensation capacitance and improvement in slew rate compared to conventional nested Miller compensation and the other reported techniques in the literature.

scholarly journals Low-Noise Chopper-Stabilized Multi-Path Operational Amplifier with Nested Miller Compensation for High-Precision Sensors

2019 ◽  
Vol 10 (1) ◽  
pp. 281 ◽  
Author(s):  
Jaesung Kim ◽  
Hyungseup Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
High Precision ◽  
Operational Amplifier ◽  
High Frequency ◽  
Flicker Noise ◽  
Low Frequency ◽  
Low Noise ◽  
Cmos Process ◽  
Miller Compensation ◽  
Chopper Stabilization ◽  
Nested Miller Compensation

This paper presents a low-noise multi-path operational amplifier for high-precision sensors. A chopper stabilization technique is applied to the amplifier to remove offset and flicker noise. A ripple reduction loop (RRL) is designed to remove the ripple generated in the process of up-modulating the flicker noise and offset. To cancel the notch in the overall transfer function due to the RRL operation, a multi-path architecture using both a low-frequency path (LFP) and high-frequency path (HFP) is implemented. The low frequency path amplifier is implemented using the chopper technique and the RRL. In the high-frequency path amplifier, a class-AB output stage is implemented to improve the power efficiency. The transfer functions of the LFP and HFP induce a first-order frequency response in the system through nested Miller compensation. The low-noise multi-path amplifier was fabricated using a 0.18 µm 1P6M complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the proposed low-noise operational amplifier is 0.174 mW with a 1.8 V supply and an active area of 1.18 mm2. The proposed low-noise amplifier has a unit gain bandwidth (UGBW) of 3.16 MHz, an input referred noise of 11.8 nV/√Hz, and a noise efficiency factor (NEF) of 4.46.

A LOW POWER CURRENT RECYCLING CONSTANT-gm RAIL-TO-RAIL OTA

2014 ◽  
Vol 23 (02) ◽  
pp. 1450022
Author(s):  
XIAO ZHAO ◽  
HUAJUN FANG ◽  
JUN XU
Keyword(s):  
Low Power ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Gain Bandwidth ◽  
Design Specifications ◽  
Rail To Rail ◽  
Dc Gain ◽  
Unity Gain ◽  
Simulation Results

A low power current recycling constant-gm rail-to-rail (RtR) OTA is presented. The proposed amplifier has the benefit of delivering the same performance while consuming half the power compared to the conventional RtR amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in CSMC standard 0.18 um CMOS process. Simulation results show that the proposed amplifier achieves 10.2 MHz unity-gain bandwidth, 59.4 dB DC gain, 4.8 V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional RtR amplifier with the same design specifications.

Gain-Based Double Feedforward Compensation for Multi-Stage Amplifiers

2021 ◽  
Vol 16 (2) ◽  
pp. 196-200
Author(s):  
Feng Xiaojia ◽  
Zhang Jun-An
Keyword(s):  
State Of The Art ◽  
Cmos Process ◽  
Phase Margin ◽  
Gain Bandwidth ◽  
Dominant Pole ◽  
Multi Stage ◽  
Large Step ◽  
Unity Gain ◽  
Compensation Technique ◽  
Simulation Results

A gain-based double feedforward compensation (GBDFC) for multi-stage amplifiers is proposed, which could be used in multi-stage OTA design. The proposed compensation technique provides two left-plane zeros to counteract with the first and second non-dominant poles of the OTA without reducing the dominant pole obviously. Meanwhile, a high slew-rate is presented in the condition of large step input signal. A three-stage Opamp prototype with the proposed technique is realized in a 0.18 yitm CMOS process. The post simulation results show that it provides a unity-gain bandwidth (GBW) of 103 MHz and phase margin (PM) of 70° with power consumption of 0.328 mW and small compensation capacitors, implying a better FOM compare with the state-of-the-art.

A CMOS Bandgap Reference with Temperature Compensation

2014 ◽  
Vol 667 ◽  
pp. 401-404
Author(s):  
Xi Chen ◽  
Liang Li ◽  
Xing Fa Huang ◽  
Xiao Feng Shen ◽  
Ming Yuan Xu
Keyword(s):  
Temperature Compensation ◽  
High Order ◽  
Cmos Process ◽  
Threshold Region ◽  
Bandgap Reference ◽  
Mos Transistor ◽  
First Order ◽  
Reference Circuit ◽  
Compensation Technique ◽  
Simulation Results

This paper has presented a bandgap reference circuit with high-order temperature compensation. The compensation technique is achieved by using MOS transistor operating in sub-threshold region for reducing high-order TC of Vbe. The circuit is designed in 0.18¦Ìm CMOS process. Simulation results show that the proposed circuit achieves 4.2 ppm/¡æ with temperature from-55 to 125 ¡æ, which is only a third than that of first-order compensated bandgap reference.

A Sub-1V High Precision CMOS Bandgap Reference

2013 ◽  
Vol 427-429 ◽  
pp. 1097-1100
Author(s):  
Qian Neng Zhou ◽  
Rong Xue ◽  
Hong Juan Li ◽  
Jin Zhao Lin ◽  
Yun Song Li ◽  
...  
Keyword(s):  
Temperature Coefficient ◽  
Power Supply ◽  
Output Voltage ◽  
Supply Voltage ◽  
Piecewise Linear ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Voltage ◽  
Compensation Technique ◽  
Simulation Results

In this paper, a low temperature coefficient bandgap voltage (BGR) is designed for A/D converter by adopting piecewise-linear compensation technique. The designed BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the PSRR of the designed BGR achieves-72.51dB, -72.49dB, and-70.58dB at 10Hz, 100Hz and 1kHz respectively. The designed BGR achieve the temperature coefficient of 1.57 ppm/°C when temperature is in the range from-35°C to 125°C. When power supply voltage VDD changes from 1V to 7V, the deviation of the designed BGR output voltage VREF is only 4.465μV.

Multistage Amplifier Using Dual-Miller with Nulling-Resistor and Dual-Feedforward Structure

2014 ◽  
Vol 989-994 ◽  
pp. 1169-1172
Author(s):  
Qian Neng Zhou ◽  
Qi Li ◽  
Jin Zhao Lin ◽  
Hong Juan Li ◽  
Chen Li ◽  
...  
Keyword(s):  
High Gain ◽  
Phase Margin ◽  
Slew Rate ◽  
Well Performance ◽  
Gain Bandwidth ◽  
Wide Bandwidth ◽  
Miller Compensation ◽  
Dc Gain ◽  
Simulation Results ◽  
Multistage Amplifier

This paper designs a high-gain wide-bandwidth multistage amplifier by employing the dual-miller compensation with nulling-resistor and dual-feedforward compensation (DMCNR-DFC) in 0.35μm BCD process. The designed DMCNR-DFC multistage amplifier achieves well performance including gain-bandwidth product (GBW) and slew rate (SR). Simulation results show that the DMCNR-DFC multistage amplifier achieves a dc gain of about 121.1dB and GBW of about 6.1MHz with 52o phase margin.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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