Optimal design of thin-profile fine-pitch ball grid array package under drop impact test

2011 ◽  
Vol 225 (12) ◽  
pp. 2775-2791 ◽  
Author(s):  
R S Chen ◽  
H E Cheng ◽  
R W Wu ◽  
C H Huang ◽  
W C Liao ◽  
...  
Keyword(s):  
Solder Ball ◽  
Ball Grid Array ◽  
Drop Test ◽  
Circuit Board ◽  
Impact Pulse ◽  
Excitation Scheme ◽  
Thin Profile ◽  
Fine Pitch ◽  
Support Excitation ◽  
The Impact

This article describes the board-level drop reliability of thin-profile fine-pitch ball grid array (TFBGA) subjected to Joint Electron Device Engineering Council (JEDEC) drop test conditions featuring an impact pulse profile with a peak acceleration of 1500  G and a pulse duration of 0.5 ms. The solder ball is assumed to be an elastoplastic model and the other components linear elastic ones. Both the global/local finite element and the finite grid region methods are introduced to improve the accuracy and the convergence during the meshing process. Meanwhile, the contact impact process during the drop test is translated into the effective support excitation load on the printed circuit board (PCB) through the support excitation scheme to simplify the analysis. By means of optimal parameters of the Taguchi robust design, the average stress of the solder ball at the PCB side surface becomes 80.9 MPa, which shows a 57 per cent reduction compared to the original stress of 189.7 MPa. As a result, the impact reliability of the TFBGA package is significantly improved. Finally, the JEDEC drop test is conducted to verify the optimal results obtained by the Taguchi method.

Numerical Simulation and Experimental Measurement of a Printed Circuit Board Subjected to Drop Test

2009 ◽  
Vol 419-420 ◽  
pp. 37-40
Author(s):  
Shiuh Chuan Her ◽  
Shien Chin Lan ◽  
Chun Yen Liu ◽  
Bo Ren Yao
Keyword(s):  
Finite Element ◽  
Experimental Measurement ◽  
Test Specimen ◽  
Printed Circuit Board ◽  
Drop Impact ◽  
Simulation Technique ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit ◽  
The Impact

Drop test is one of the common methods for determining the reliability of electronic products under actual transportation conditions. The aim of this study is to develop a reliable drop impact simulation technique. The test specimen of a printed circuit board is clamped at two edges on a test fixture and mounted on the drop test machine platform. The drop table is raised at the height of 50mm and dropped with free fall to impinge four half-spheres of Teflon. One accelerometer is mounted on the center of the specimen to measure the impact pulse. The commercial finite element software ANSYS/LS-DYNA is applied to compute the impact acceleration and dynamic strain on the test specimen during the drop impact. The finite element results are compared to the experimental measurement of acceleration with good correlation between simulation and drop testing. With the accurate simulation technique, one is capable of predicting the impact response and characterizing the failure mode prior to real reliability test.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

Material Issues of Low Temperature Co-fired Ceramic (LTCC) Fine Pitch Chip Scale Package (CSP) Designs

2003 ◽  
Vol 783 ◽  
Author(s):  
Megan M. Owens ◽  
Joseph W. Soucy ◽  
Thomas F. Marinis ◽  
Kevin A. Bruff ◽  
Henry G. Clausen
Keyword(s):  
Shear Test ◽  
Solder Ball ◽  
Ball Grid Array ◽  
Substrate Material ◽  
Test Results ◽  
Shear Tests ◽  
Fine Pitch ◽  
Test Board ◽  
Chip Scale Package ◽  
Ltcc Substrate

ABSTRACTLTCC substrates for fine pitch (1.0 mm and 0.8 mm) CSP applications have been designed, fabricated, and assembled. The assembly process, including ball grid array (BGA) solder ball attach, die mount, wire bond, and glob top is described. The material and physical design interaction issues that emerged during development are discussed.The initial CSP design was conventional, with co-fired yellow gold (Au) vias and capture pads and post-fired solderable gold (PtPdAu) pads for solder ball attachment. Because LTCC tape shrinks during co-fire, solder pads were applied post co-fire to ensure proper mating with existing test fixtures and to provide the best alignment relative to the CSP body. Solder pad to capture pad misalignment was visible following solder pad firing. After CSP attachment to a test board, electrical tests revealed opens. Investigation led to the following conclusions. The decreased solder pad diameter necessary to accommodate the fine pitch design was significant relative to the area allocated for the underlying via and capture pad. Misalignment that would have been hidden under larger solder pads was exposed. Even when the capture pad surface was not visibly exposed, the offset solder pad meant less material between the capture pad and the solder ball, less of a barrier to solder leaching. Solder leaching into the yellow gold, observed after CSP removal from the test board, was the cause of the electrical disconnects. In the second design, the capture pad was eliminated in order to discourage leaching by reducing the volume of yellow gold available to alloy with the solder pad during co-fire. Reflow operations still resulted in leached solder pads. A third design replaced the first-layer via yellow gold with a solderable gold. This design proved to be robust.While developing designs and fabricating these prototypes, it was noted that all ball failures consistently occurred between the solder pad and the LTCC substrate. To investigate adhesion using different metallizations, shear tests were performed on LTCC substrates with either post-fired solder pads or co-fired pads. To investigate how the substrate material affects adhesion, alumina CSPs were also sheared. Shear test results are presented.

Finite Element Prediction of Stack-Die Packages under Board Level Drop Test

2008 ◽  
Vol 594 ◽  
pp. 169-174
Author(s):  
Hsiang Chen Hsu ◽  
Yu Chia Hsu ◽  
Chan Lin Yeh ◽  
Yi Shao Lai
Keyword(s):  
Solder Joint ◽  
Equivalent Stress ◽  
Drop Test ◽  
Excitation Scheme ◽  
Joint Reliability ◽  
Solder Balls ◽  
Mesh Density ◽  
Parametric Studies ◽  
Support Excitation ◽  
Board Level

The objective of this research is to investigate the solder joint reliability of board-level drop test based on the support excitation scheme incorporated with the submodel technique for stacked-die packages. Three lead-free materials, SAC405 (Sn4Ag0.5Cu), SAC355(Sn3.5Ag0.5Cu) and Sn3.5Ag were used to demonstrate the transient dynamic response for solder balls subject to JEDEC pulse-controlled board-level drop test standard. In order to evaluate the structure of the interested area, a strip model sliced from the full test vehicle is used in this research. In addition, the submodel region is particularly chosen with strip model by performing the cut boundary interpolation. The envelope of equivalent stress for the outermost solder joint off the end of the strip model is plot to show the potential failure mode and mechanism. The cut boundary of submodel is verified and the mesh density of submodel is examined. For a refinery mesh of submodel, parametric studies for structure and material are carried out to investigate the reliability of the outermost solder joint, and the results are summarized as design rules for the development of stacked-die packages.

scholarly journals DDR4 BER Degradation Due to Crack in FBGA Package Solder Ball

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1445
Author(s):  
Muhammad Waqar ◽  
Geunyong Bak ◽  
Junhyeong Kwon ◽  
Sanghyeon Baeg
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Solder Ball ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Thermal Coefficient ◽  
Electrical Model ◽  
Fine Pitch ◽  
Solder Balls ◽  
Board Material

This paper measures bit error rate degradation in DDR4 due to crack in fine pitch ball grid array (FBGA) package solder ball. Thermal coefficient mismatch between the package and printed circuit board material causes cracks to occur in solder balls. These cracks change the electrical model of the solder ball and introduce parallel capacitance in the electrical model. The capacitance causes higher frequency attenuation and closes the data eye. As the data rate of the DDR4 increases there are more data eye closures. The data eye closure causes bit error rate (BER) degradation as the timing margin and voltage margin decreases. This degradation reduces the reliability of the system and causes more intermittent errors. DDR4 data line is loaded with a parallel capacitive element to mimic a crack in solder ball. The measured data eye shows a decrease in eye width. Bathtub plots are created for comparison of cracked solder ball and intact solder ball. The bathtub plots show the BER degradation due to crack in solder ball.

The influence of solder composition on the impact strength of lead-free solder ball grid array joints

2011 ◽  
Vol 51 (3) ◽  
pp. 657-667 ◽  
Author(s):  
H. Tsukamoto ◽  
T. Nishimura ◽  
S. Suenaga ◽  
S.D. McDonald ◽  
K.W. Sweatman ◽  
...  
Keyword(s):  
Impact Strength ◽  
Solder Ball ◽  
Ball Grid Array ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder ◽  
The Impact ◽  
Solder Composition

The Effect of Ball Pad Metallurgy and Ball Composition on Solder Ball Integrity of Plastic Ball Grid Array Packages

1998 ◽  
Author(s):  
C.H. Zhong ◽  
Sung Yi
Keyword(s):  
Failure Mode ◽  
Barrier Layer ◽  
Shear Force ◽  
Solder Ball ◽  
Ball Grid Array ◽  
Reliability Test ◽  
Shear Forces ◽  
Ball Shear ◽  
Plastic Ball ◽  
Plastic Ball Grid Array

Abstract Ball shear forces of plastic ball grid array (PBGA) packages are found to decrease after reliability test. Packages with different ball pad metallurgy form different intermetallic compounds (IMC) thus ball shear forces and failure modes are different. The characteristic and dynamic process of IMC formed are decided by ball pad metallurgy which includes Ni barrier layer and Au layer thickness. Solder ball composition also affects IMC formation dynamic process. There is basically no difference in ball shear force and failure mode for packages with different under ball pad metallurgy before reliability test. However shear force decreased and failure mode changed after reliability test, especially when packages exposed to high temperature. Major difference in ball shear force and failure mode was found for ball pad metallurgy of Ni barrier layer including Ni-P, pure Ni and Ni-Co. Solder ball composition was found to affect the IMC formation rate.

scholarly journals Eco-Friendly Lead-Free Solder Paste Printing via Laser-Induced Forward Transfer for the Assembly of Ultra-Fine Pitch Electronic Components

Materials ◽  
2021 ◽  
Vol 14 (12) ◽  
pp. 3353
Author(s):  
Marina Makrygianni ◽  
Filimon Zacharatos ◽  
Kostas Andritsos ◽  
Ioannis Theodorakos ◽  
Dimitris Reppas ◽  
...  
Keyword(s):  
High Resolution ◽  
Form Factors ◽  
Circuit Board ◽  
Lead Free ◽  
Process Conditions ◽  
Solder Paste ◽  
Electronic Components ◽  
Successful Operation ◽  
Fine Pitch ◽  
Forward Transfer

Current challenges in printed circuit board (PCB) assembly require high-resolution deposition of ultra-fine pitch components (<0.3 mm and <60 μm respectively), high throughput and compatibility with flexible substrates, which are poorly met by the conventional deposition techniques (e.g., stencil printing). Laser-Induced Forward Transfer (LIFT) constitutes an excellent alternative for assembly of electronic components: it is fully compatible with lead-free soldering materials and offers high-resolution printing of solder paste bumps (<60 μm) and throughput (up to 10,000 pads/s). In this work, the laser-process conditions which allow control over the transfer of solder paste bumps and arrays, with form factors in line with the features of fine pitch PCBs, are investigated. The study of solder paste as a function of donor/receiver gap confirmed that controllable printing of bumps containing many microparticles is feasible for a gap < 100 μm from a donor layer thickness set at 100 and 150 μm. The transfer of solder bumps with resolution < 100 μm and solder micropatterns on different substrates, including PCB and silver pads, have been achieved. Finally, the successful operation of a LED interconnected to a pin connector bonded to a laser-printed solder micro-pattern was demonstrated.

Sign in / Sign up

Export Citation Format

Share Document