scholarly journals DDR4 BER Degradation Due to Crack in FBGA Package Solder Ball

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1445
Author(s):  
Muhammad Waqar ◽  
Geunyong Bak ◽  
Junhyeong Kwon ◽  
Sanghyeon Baeg
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Solder Ball ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Thermal Coefficient ◽  
Electrical Model ◽  
Fine Pitch ◽  
Solder Balls ◽  
Board Material

This paper measures bit error rate degradation in DDR4 due to crack in fine pitch ball grid array (FBGA) package solder ball. Thermal coefficient mismatch between the package and printed circuit board material causes cracks to occur in solder balls. These cracks change the electrical model of the solder ball and introduce parallel capacitance in the electrical model. The capacitance causes higher frequency attenuation and closes the data eye. As the data rate of the DDR4 increases there are more data eye closures. The data eye closure causes bit error rate (BER) degradation as the timing margin and voltage margin decreases. This degradation reduces the reliability of the system and causes more intermittent errors. DDR4 data line is loaded with a parallel capacitive element to mimic a crack in solder ball. The measured data eye shows a decrease in eye width. Bathtub plots are created for comparison of cracked solder ball and intact solder ball. The bathtub plots show the BER degradation due to crack in solder ball.

The Die Embedded and RDL structure on the high density substrate (i-THOP®) for mobile application

2016 ◽  
Vol 2016 (1) ◽  
pp. 000001-000006
Author(s):  
Masahiro Kyozuka ◽  
Tatsuro Yoshida ◽  
Noriyoshi Shimizu ◽  
Koichi Tanaka ◽  
Tetsuya Koyama
Keyword(s):  
Mobile Devices ◽  
Manufacturing Process ◽  
Printed Circuit Board ◽  
Semiconductor Device ◽  
Current Trend ◽  
High Density ◽  
Circuit Board ◽  
Fine Pitch ◽  
Package Size ◽  
Proper Material

Abstract The current trend in the electronics industry is one of increased computing performance, combined with a seemingly unending demand for portability and increased miniaturization; this is especially evident in the significant changes to the semiconductor device. To sustain the performance-improvement trend without increasing total cost, the partitioning of single die into a multi-chip architecture is widely studied in industry. These partitioned chips are then integrated into a single system-in-package (SiP). However, partitioning a single die into multiple split die causes two major challenges. The first is that it creates the need for very high density die to die interconnection. This interconnection is needed to provide enough routing density between the multiple die. Based on design studies, it believes that 2μm line and 2μm space is required in the package substrate. The second challenge is created by the increase in the overall die size. After partitioning the single die, each resulting smaller die must have its own I/O circuits, and effectively increases the total die area. This increase is a penalty, as mobile devices have a limited package size. When comparing a conventional package on package (PoP), the SiP requires a higher pin count with a finer pitch connection between the die and the memory. This finer pitch is needed to have enough I/Os, but within a limited package size to support mobile devices. To overcome these challenges, the structure of i-THOP® with POP pad, named “i-THOP® with Die embedded +ReDestribution Layer(RDL) structure”, has been developed. Herein, i-THOP® (integrated Thin film High density Organic Package) is a type of high-density substrate A key aspect to development of Die embedded +RDL is forming the multiple redistribution layers (RDL) over die and the fine pitch via connection. To achieve this, the proper material set was selected based on stress simulations and basic experiments. Regarding the manufacturing process, a conventional printed-circuit board (PCB) production line was used to minimize production cost. This article reports the manufacturing process and characteristics of the structure.

Estimation Of Complex Permittivity Of Printed Circuit Board Material Using Waveguide Measurements

1996 ◽  
Vol 430 ◽  
Author(s):  
C. J. Reddy ◽  
M. D. Deshpande ◽  
G. A. Hanidu
Keyword(s):  
Dielectric Constant ◽  
Reflection Coefficient ◽  
Complex Permittivity ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
The Finite Element Method ◽  
Printed Circuit ◽  
X Band ◽  
Board Material ◽  
Raphson Method

AbstractA simple waveguide measurement technique is presented to determine the complex permittivity of printed circuit board material. The printed circuit board with metal coating removed from both sides and cut into size which is the same as the cross section of the waveguide is loaded in a short X-band rectangular waveguide. Using a network analyzer, the reflection coefficient of the shorted waveguide(loaded with the sample) is measured. Using the Finite Element Method(FEM) the exact reflection coefficient of the shorted wavguide(loaded with the sample) is determined as a function of dielectric constant. Matching the measured value of the reflection coefficient with the reflection value calculated using FEM and utilizing Newton-Raphson Method, an estimate of the dielectric constant of a printed circuit board material is obtained. A comparison of estimated values of permittivity constant obtained using the present approach with the available data.

Causes of Degradation of Thermal Performance of Ball Grid Arrays After Thermal Cycling

2007 ◽  
Author(s):  
Roy W. Knight ◽  
Yasser Elkady ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall
Keyword(s):  
Solder Joint ◽  
Thermal Resistance ◽  
Thermal Cycling ◽  
Thermal Performance ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Element Analysis ◽  
Solder Balls ◽  
Ball Grid Array Packages ◽  
The Impact

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA’s was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from −40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. Finite element analysis identified critical thermal and perimeter solder balls as the most likely sites for cracking. Boards were cross-sectioned and examined for solder joint cracks and delamination to identify the cause for the observed increases in thermal resistance. Cracking was found in the critical thermal and perimeter solder balls.

Packaging Challenges of Thin High Bandwidth POP

2019 ◽  
Author(s):  
Fletcher (Cheng-Piao) Tung ◽  
Jensen (Ying-Chou) Tsai ◽  
Yu-Po Wang ◽  
Joe (Chih-Nan) Lin ◽  
Gary (Yue-Long) Fan
Keyword(s):  
Printed Circuit Board ◽  
Lower Cost ◽  
Coefficient Of Thermal Expansion ◽  
Cellular Phone ◽  
Circuit Board ◽  
Printed Circuit ◽  
Fine Pitch ◽  
High Bandwidth ◽  
Application Processor ◽  
Different Thickness

Abstract Components for Smartphone has been the biggest driving force of IC industry for years, and one of the most important IC is application processor (AP). AP needs to work with low power double data rate (LPDDR), the mobile DRAM together for the primary processing of cellular phone and other smart functions. At the beginning, they were packaged separately and then mounted onto printed circuit board (PCB) very close to each other. Nowadays, AP for flagship Smartphone is packaged with a variety of PoP (package on package) structures to shorten the communication distance between AP and LPDDR as well as to save more rooms for battery. High bandwidth package on package (HBW-POP) is the most popular structure among them. As compared to other substrate based PoP, HBW-POP provides the most top side pin count while keeps larger ball pitch for system assembly house to mount LPDDR packaged by fine-pitch ball grid array (FBGA) on top of it. And compared to novel Fan-Out based PoP, HBW-POP has lower cost for AP packaging. In addition, maximum package height of HBW-POP has been shrinking. It is because when LPDDR is mounted onto HBW-POP, the combination is always the tallest chips on the PCB, which determines how slim specific Smartphone can be. HBW-POP consists of 3 parts to encapsulate AP die, and they are top 2-layer substrate, middle molding and bottom 3-layer substrate. Each part has its own coefficient of thermal expansion (CTE) and rigidity, and the warpage performance of HBW-POP is important to align the warpage behavior of LPDDR. The warpage of HBW-POP needs to align with FBGA properly during reflow for good joint, but when HBW-POP becomes thinner, the rigidity of its different parts is changed, which result in different warpage behavior during the reflow. In this paper, we will review the challenges of thin HBW-POP packaging, meanwhile we will explore possible solutions to address each challenge. The study includes the screening of different thickness combination of the 3 parts of HBW-POP, and the optimization of the rigidity and CTE of them. Design of Experiments (DOE) are conducted to find solutions which can meet warpage target, and finally, we present more different tests to prove the reliability of our results.

PCB Pad Cratering – Characterization Techniques and Challenges

2008 ◽  
Author(s):  
Satish Parupalli ◽  
Keith Newman ◽  
Mudasir Ahmad
Keyword(s):  
Working Group ◽  
Solder Ball ◽  
Printed Circuit Board ◽  
Phase 1 ◽  
Test Methods ◽  
Circuit Board ◽  
Mechanical Fracture ◽  
Characterization Techniques ◽  
Pad Cratering ◽  
Phase 2 Study

Abstract Some standard characterization techniques (solder ball pull, solder ball shear, etc.) exist for the assessment of solder ball mechanical fracture strength; however, it is not clear if these test methods would also provide characterization of printed circuit board (PCB) pad cratering susceptibility. This paper provides an overview of test methods being investigated by a PCB pad crater industry working group. The scope of this industry working group is two-fold: standardization of PCB pad crater crack characterization and measurement methods and development of a quantitative quality metric for PCB pad cratering. Though the test methods were successful in creating pad craters; there was not enough distinction between the various laminate material types based on the output parameters. Based on the readings from Phase 1 study and available literature, the team is in the process of completing the Phase 2 study which will be reported at a later stage.

Optimal design of thin-profile fine-pitch ball grid array package under drop impact test

2011 ◽  
Vol 225 (12) ◽  
pp. 2775-2791 ◽  
Author(s):  
R S Chen ◽  
H E Cheng ◽  
R W Wu ◽  
C H Huang ◽  
W C Liao ◽  
...  
Keyword(s):  
Solder Ball ◽  
Ball Grid Array ◽  
Drop Test ◽  
Circuit Board ◽  
Impact Pulse ◽  
Excitation Scheme ◽  
Thin Profile ◽  
Fine Pitch ◽  
Support Excitation ◽  
The Impact

This article describes the board-level drop reliability of thin-profile fine-pitch ball grid array (TFBGA) subjected to Joint Electron Device Engineering Council (JEDEC) drop test conditions featuring an impact pulse profile with a peak acceleration of 1500  G and a pulse duration of 0.5 ms. The solder ball is assumed to be an elastoplastic model and the other components linear elastic ones. Both the global/local finite element and the finite grid region methods are introduced to improve the accuracy and the convergence during the meshing process. Meanwhile, the contact impact process during the drop test is translated into the effective support excitation load on the printed circuit board (PCB) through the support excitation scheme to simplify the analysis. By means of optimal parameters of the Taguchi robust design, the average stress of the solder ball at the PCB side surface becomes 80.9 MPa, which shows a 57 per cent reduction compared to the original stress of 189.7 MPa. As a result, the impact reliability of the TFBGA package is significantly improved. Finally, the JEDEC drop test is conducted to verify the optimal results obtained by the Taguchi method.

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