A 3D Analytic Modeling of Threshold Voltages of FD SOI MOSFET

This work investigates the X-ray irradiation impact on the performance of an on-conventional transistor called OCTO SOI MOSFET that adopts an octagonal gate shape instead of a rectangular. The electrical behaviors of both devices were studied through an experimental comparative analysis of the total ionizing dose influence. In addition, the back-gate bias technique was applied in these devices to reestablish its threshold voltages and drain currents conditions that were degraded due the trapping of positive charges in the buried oxide. As the main finding of this work, after the irradiation procedure, we notice that the OCTO device is capable to reestablish its pre-rad electrical behavior with a smaller back gate bias than the one observed in the standard one counterpart. This is mainly because the parasitic transistors in the bird’s beak region are practically deactivated due the particular octagonal gate geometry.

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Simulação analítica de espelhos de corrente utilizando associação série do transistores SOI MOSFET

10.31414/ee.2020.d.131163 ◽

2020 ◽

Author(s):

◽

Paulo Rodrigues Silva

Keyword(s):

Open Loop ◽

Common Source ◽

Model Parameters ◽

Current Mirror ◽

Soi Mosfet ◽

Current Mirrors ◽

Threshold Voltages ◽

Analog Blocks ◽

Self Cascode ◽

Output Conductance

This work presents an analysis of the advantages of symmetric (S-SC) and asymmetric (A-SC) self-cascode associations of nMOSFETs in relation to a single transistor (ST) SOI MOSFET by means of analytical simulations of basic analog blocks. Besides presenting the characteristics of a single transistor amplifier, current mirrors with different architectures are studied. The study and evaluation of these analog blocks were performed based on electricals characteristics obtained from SPICE circuits simulations, using ICAP/4 software. Initially, model parameters were adjusted to fit experimental data, to ensure simulated devices characteristics similar to the real ones. After these adjustments, symmetric self-cascode (association of two transistors with identical threshold voltages) and asymmetric self-cascode (association of two transistors with different threshold voltages) of SOI nMOSFETs were simulated at device level. Electrical parameters such as drain current (IDS), transconductance (gm), output conductance (gD), Early voltage (VEA), open loop gain voltage and gm/IDS ratio are presented as a function of the voltage applied to single transistor terminals and composite device (symmetric and asymmetric associations) with different dimensions. Then, the series associations and the single transistors (ST) were used in current mirrors circuits in CommonSource and single transistor in Cascode and Wilson architectures to verify the composed structure performance. It has been verified that current mirror using association S-SC present electrical behavior similar to the current mirror formed by SOI MOSFET ST, with the same channel length. It has been observed that the association A-SC features better electric performance in relation to the S-SC and ST in common-source current mirror, as well, in relation to Cascode and Wilson architectures using single transistors, in week and moderate inversion regions, due to the better output conductance and, consequently, the higher Early voltage

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An Analytical Model for Deriving the 3-D Potentials and the Front and Back Gate Threshold Voltages of a Mesa-Isolated Small Geometry Fully Depleted SOI MOSFET

JSTS Journal of Semiconductor Technology and Science ◽

10.5573/jsts.2012.12.4.473 ◽

2012 ◽

Vol 12 (4) ◽

pp. 473-481

Author(s):

Jae Bin Lee ◽

Chung Ha Suh

Keyword(s):

Analytical Model ◽

Back Gate ◽

Fully Depleted ◽

Soi Mosfet ◽

Threshold Voltages

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Microstructure studies of tungsten silicide schottky contacts on Gaas

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100126445 ◽

1987 ◽

Vol 45 ◽

pp. 328-329

Author(s):

Yih-Cheng Shih ◽

E. L. Wilkie

Keyword(s):

Thermal Stability ◽

Field Effect Transistors ◽

Schottky Contact ◽

Schottky Contacts ◽

Excellent Thermal Stability ◽

Barrier Heights ◽

Gaas Substrates ◽

Film Adhesion ◽

Threshold Voltages ◽

Thermal Stability Of

Tungsten silicides (WSix) have been successfully used as the gate materials in self-aligned GaAs metal-semiconductor-field- effect transistors (MESFET). Thermal stability of the WSix/GaAs Schottky contact is of major concern since the n+ implanted source/drain regions must be annealed at high temperatures (∼ 800°C). WSi0.6 was considered the best composition to achieve good device performance due to its low stress and excellent thermal stability of the WSix/GaAs interface. The film adhesion and the uniformity in barrier heights and ideality factors of the WSi0.6 films have been improved by depositing a thin layer of pure W as the first layer on GaAs prior to WSi0.6 deposition. Recently WSi0.1 has been used successfully as the gate material in 1x10 μm GaAs FET's on the GaAs substrates which were sputter-cleaned prior to deposition. These GaAs FET's exhibited uniform threshold voltages across a 51 mm wafer with good film adhesion after annealing at 800°C for 10 min.

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A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.2764 ◽

2017 ◽

Vol E100.A (12) ◽

pp. 2764-2775 ◽

Cited By ~ 1

Author(s):

Jun SHIOMI ◽

Tohru ISHIHARA ◽

Hidetoshi ONODERA

Keyword(s):

Minimum Energy ◽

Cmos Circuits ◽

Sufficient Condition ◽

Necessary And Sufficient Condition ◽

Energy Point ◽

Threshold Voltages ◽

Necessary And Sufficient ◽

Minimum Energy Point

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An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

Nanoscience &Nanotechnology-Asia ◽

10.2174/2210681208666180820151121 ◽

2019 ◽

Vol 9 (4) ◽

pp. 504-511

Author(s):

Sikha Mishra ◽

Urmila Bhanja ◽

Guru Prasad Mishra

Keyword(s):

Analytical Model ◽

Surface Potential ◽

Threshold Voltage ◽

Silicon On Insulator ◽

Junction Depth ◽

Short Channel ◽

Soi Mosfet ◽

Minimum Surface ◽

Recessed Channel ◽

The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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