Wires, switches, and wiring. A route toward a chemically assembled electronic nanocomputer

2000 ◽  
Vol 72 (1-2) ◽  
pp. 11-20 ◽  
Author(s):  
James R. Heath
Keyword(s):  
Power Consumption ◽  
Hierarchical Organization ◽  
Boolean Logic ◽  
High Yield ◽  
Collaborative Effort ◽  
Hewlett Packard ◽  
Field Programmable ◽  
Read Only Memory ◽  
Logic Structures ◽  
Molecular Compounds

A Boolean logic, nonreversible computing machine should, in principle, be capable of 10 18 bit operations per second at a power consumption of 1 W. In order to build such a machine that can even approach this benchmark for efficiency, the development of a robust quantum-state switch capable of ambient operation, as well as a bottom–up manufacturing technology, will be necessary. My group, in collaboration with Hewlett Packard, has developed much of the architecture for such a machine, which we call a chemically assembled electronic nanocomputer (CAEN). More recently, in a collaborative effort with Fraser Stoddart's group at UCLA, we have begun to build it. The fundamental unit of the machine is a field-programmable molecular switch, and the fundamental architecture is a hierarchical organization of wire/switch lattices called crossbars. Electronically, singly configurable molecular-based switch devices based on rotaxane molecular compounds have been fabricated in high yield. These switches were used to construct simple molecular-based logic structures and read-only memory elements.

scholarly journals High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

2018 ◽  
Vol 7 (4) ◽  
pp. 2569
Author(s):  
Priyanka Chauhan ◽  
Dippal Israni ◽  
Karan Jasani ◽  
Ashwin Makwana
Keyword(s):  
Power Consumption ◽  
Data Acquisition ◽  
Resource Utilization ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
State Of The Art ◽  
Data Rate ◽  
Field Programmable ◽  
Sensor Signals ◽  
Acquisition Technique

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.  

scholarly journals On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Switching Scheme ◽  
Fpga Design ◽  
Gate Arrays ◽  
Magnetic Switching ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Time Required ◽  
Magnetic Tunneling

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

Built-In Self Repair for Logic Structures

2014 ◽  
pp. 1376-1402
Author(s):  
Tobias Koal ◽  
Heinrich T. Vierhaus
Keyword(s):  
Software Systems ◽  
Gate Arrays ◽  
Regular Structures ◽  
Permanent Faults ◽  
Integrated Devices ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Self Repair ◽  
Logic Structures ◽  
Time Of Operation

For several years, many authors have predicted that nano-scale integrated devices and circuits will have a rising sensitivity to both transient and permanent faults effects. Essentially, there seems to be an emerging demand for building highly dependable hardware / software systems from unreliable components. Most of the effort has so far gone into the detection and compensation of transient fault effects. More recently, also the possibility of repairing permanent faults, due to either production flaws or to wear-out effects after some time of operation in the field of application, needs further investigation. While built-in self test (BIST) and even self repair (BISR) for regular structures such as static memories (SRAMs) is well understood, concepts for in-system repair of irregular logic and interconnects are few and mainly based on field-programmable gate-arrays (FPGAs) as the basic implementation. In this chapter, the authors try to analyse different schemes of logic (self-) repair with respect to cost and limitations, using repair schemes that are not based on FPGAs. It can be shown that such schemes are feasible, but need lot of attention in terms of hidden single points of failure.

Challenges in 3D Inspection of Micro Bumps Used in 3D Packaging

2012 ◽  
Vol 2012 (1) ◽  
pp. 000542-000547 ◽  
Author(s):  
Reza Asgari
Keyword(s):  
Power Consumption ◽  
Wafer Bonding ◽  
Field Programmable Gate Array ◽  
Laser Triangulation ◽  
3D Measurement ◽  
Lower Power ◽  
Small Pitch ◽  
Field Programmable ◽  
3D Packaging ◽  
2D And 3D

2.5D/3D devices are the next major packaging technologies, driven by the need for more functionality, lower power consumption and smaller footprint. Many device manufacturers are devoting capital to develop their own processes and some are already shipping devices such as FPGA (Field Programmable Gate Array) on interposers. 3D packages often require hundreds of thousands of I/O per die. Micro Pillar bumps and C4 bumps are the main bump geometries used in 3D packages as their small pitch and size allow the required number of I/Os. Inspecting these bumps throughout the process is critical because failure after chip to chip or chip to wafer bonding is very costly. This paper describes the use of a camera and laser triangulation to provide complete 2D and 3D measurement and inspection capability.

scholarly journals FPGA Realization of Deep Neural Network for Hardware Trojan Detection

2020 ◽  
Vol 9 (3) ◽  
pp. 764
Author(s):  
Varun Reddy ◽  
Nirmala Devi M
Keyword(s):  
Neural Network ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Deep Neural Network ◽  
Random Forest Classifier ◽  
Third Party ◽  
Hardware Trojan ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Field Programmable

With the increase in outsourcing design and fabrication, malicious third-party vendors often insert hardware Trojan (HT) in the integrated Circuits(IC). It is difficult to identify these Trojans since the nature and characteristics of each Trojan differ significantly. Any method developed for HT detection is limited by its capacity on dealing with varied types of Trojans. The main purpose of this study is to show using deep learning (DL), this problem can be dealt with some extent and the effect of deep neural network (DNN) when it is realized on field programmable gate array (FPGA). In this paper, we propose a comparison of accuracy in finding faults on ISCAS’85 benchmark circuits between random forest classifier and DNN. Further for the faster processing time and less power consumption, the network is implemented on FPGA. The results show the performance of deep neural network gets better when a large number of nets are used and faster in the execution of the algorithm. Also, the speedup of the neuron is 100x times better when implemented on FPGA with 15.32% of resource utilization and provides less power consumption than GPU.

scholarly journals Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem

2021 ◽  
Vol 11 (4) ◽  
pp. 43
Author(s):  
Bikash Poudel ◽  
Arslan Munir ◽  
Joonho Kong ◽  
Muazzam A. Khan
Keyword(s):  
Elliptic Curve ◽  
Acoustic Analysis ◽  
Fitness Function ◽  
Scalar Multiplication ◽  
Fault Analysis ◽  
Boolean Logic ◽  
Side Channel ◽  
Elliptic Curve Cryptosystem ◽  
Non Invasive ◽  
Field Programmable

The elliptic curve cryptosystem (ECC) has been proven to be vulnerable to non-invasive side-channel analysis attacks, such as timing, power, visible light, electromagnetic emanation, and acoustic analysis attacks. In ECC, the scalar multiplication component is considered to be highly susceptible to side-channel attacks (SCAs) because it consumes the most power and leaks the most information. In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L) circuit. We then design point-addition and point-doubling circuits using the same procedure. Finally, we integrate these components together into a complete secure and dependable ECC processor. We design and validate the ECC processor using Xilinx ISE 14.7 and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA).

scholarly journals Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 23-26
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Control Unit ◽  
Input Output ◽  
Green Communication ◽  
Power Efficient ◽  
Efficient Control ◽  
Field Programmable

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

scholarly journals Implementation of Blockchain Consensus Algorithm on Embedded Architecture

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Tarek Frikha ◽  
Faten Chaabane ◽  
Nadhir Aouinti ◽  
Omar Cheikhrouhou ◽  
Nader Ben Amor ◽  
...  
Keyword(s):  
Power Consumption ◽  
Execution Time ◽  
Autonomous Systems ◽  
Consensus Algorithm ◽  
Iot Applications ◽  
Novel Approach ◽  
Field Programmable ◽  
Positive Rate ◽  
Iot Devices ◽  
The Cost

The adoption of Internet of Things (IoT) technology across many applications, such as autonomous systems, communication, and healthcare, is driving the market’s growth at a positive rate. The emergence of advanced data analytics techniques such as blockchain for connected IoT devices has the potential to reduce the cost and increase in cloud platform adoption. Blockchain is a key technology for real-time IoT applications providing trust in distributed robotic systems running on embedded hardware without the need for certification authorities. There are many challenges in blockchain IoT applications such as the power consumption and the execution time. These specific constraints have to be carefully considered besides other constraints such as number of nodes and data security. In this paper, a novel approach is discussed based on hybrid HW/SW architecture and designed for Proof of Work (PoW) consensus which is the most used consensus mechanism in blockchain. The proposed architecture is validated using the Ethereum blockchain with the Keccak 256 and the field-programmable gate array (FPGA) ZedBoard development kit. This implementation shows improvement in execution time of 338% and minimizing power consumption of 255% compared to the use of Nvidia Maxwell GPUs.

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